2017-12-07 20:30:02 +01:00
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/****************************************************************************
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* arch/arm/src/lpc54628/lpc54_clockconfig.c
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*
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* Copyright (C) 2017 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Parts of this file were adapted from sample code provided for the LPC54xx
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* family from NXP which has a compatible BSD license.
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*
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* Copyright (c) 2016, Freescale Semiconductor, Inc.
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* Copyright (c) 2016 - 2017 , NXP
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <debug.h>
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#include <nuttx/arch.h>
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#include <arch/board/board.h>
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#include "up_arch.h"
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#include "up_internal.h"
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#include "chip/lpc54_syscon.h"
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#include "lpc54_power.h"
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#include "lpc54_clockconfig.h"
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: lpc54_setvoltage
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*
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* Description:
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* Set voltage for PLL frequency.
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*
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****************************************************************************/
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static void lpc54_setvoltage(uint32_t freq)
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{
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if (freq == 12000000)
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{
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putreg32(0x21e, 0x40020040);
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2017-12-10 15:54:24 +01:00
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putreg32(4, LPC54_SYSCON_PDRUNCFGSET0);
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2017-12-07 20:30:02 +01:00
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}
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else if (freq == 48000000)
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{
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putreg32(0x31e, 0x40020040);
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2017-12-10 15:54:24 +01:00
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putreg32(4, LPC54_SYSCON_PDRUNCFGSET0);
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2017-12-07 20:30:02 +01:00
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}
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else
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{
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2017-12-10 15:54:24 +01:00
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putreg32(4, LPC54_SYSCON_PDRUNCFGCLR0);
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2017-12-07 20:30:02 +01:00
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}
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}
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/****************************************************************************
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* Name: lpc54_power_pll
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*
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* Description:
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* Provide VD3 power to the PLL
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*
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****************************************************************************/
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static void lpc54_power_pll(void)
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{
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2017-12-15 00:29:15 +01:00
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lpc54_vd3_powerup();
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2017-12-07 20:30:02 +01:00
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while ((getreg32(0x40020054) & (1 << 6)) == 0)
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{
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}
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}
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/****************************************************************************
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* Name: lpc54_set_flash_waitstates
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*
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* Description:
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* Set the FLASH wait states for the passed frequency
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*
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****************************************************************************/
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static void lpc54_set_flash_waitstates(uint32_t freq)
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{
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uint32_t regval;
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regval = getreg32(LPC54_SYSCON_FLASHCFG);
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regval &= ~SYSCON_FLASHCFG_FLASHTIM_MASK;
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if (freq <= 12000000)
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{
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regval |= SYSCON_FLASHCFG_FLASHTIM(1);
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}
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else if (freq <= 24000000)
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{
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regval |= SYSCON_FLASHCFG_FLASHTIM(2);
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}
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else if (freq <= 36000000)
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{
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regval |= SYSCON_FLASHCFG_FLASHTIM(3);
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}
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else if (freq <= 60000000)
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{
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regval |= SYSCON_FLASHCFG_FLASHTIM(4);
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}
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else if (freq <= 96000000)
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{
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regval |= SYSCON_FLASHCFG_FLASHTIM(5);
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}
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else if (freq <= 120000000)
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{
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regval |= SYSCON_FLASHCFG_FLASHTIM(6);
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}
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else if (freq <= 144000000)
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{
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regval |= SYSCON_FLASHCFG_FLASHTIM(7);
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}
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else if (freq <= 168000000)
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{
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regval |= SYSCON_FLASHCFG_FLASHTIM(8);
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}
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else
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{
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regval |= SYSCON_FLASHCFG_FLASHTIM(9);
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}
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putreg32(regval, LPC54_SYSCON_FLASHCFG);
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}
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/****************************************************************************
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* Name: lpc54_configure_pll
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*
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* Description:
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* Configure the PLL.
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*
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*****************************************************************************/
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static void lpc54_configure_pll(FAR const struct pll_setup_s *pllsetup)
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{
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/* Enable power VD3 for PLLs */
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lpc54_power_pll();
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/* Power off PLL during setup changes */
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2017-12-15 00:29:15 +01:00
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lpc54_syspll_powerdown();
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2017-12-07 20:30:02 +01:00
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/* Write PLL setup data */
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putreg32(pllsetup->pllctrl, LPC54_SYSCON_SYSPLLCTRL);
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putreg32(pllsetup->pllndec, LPC54_SYSCON_SYSPLLNDEC);
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putreg32(pllsetup->pllndec | SYSCON_SYSPLLNDEC_NREQ,
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LPC54_SYSCON_SYSPLLNDEC);
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putreg32(pllsetup->pllpdec, LPC54_SYSCON_SYSPLLPDEC);
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putreg32(pllsetup->pllpdec | SYSCON_SYSPLLPDEC_PREQ,
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LPC54_SYSCON_SYSPLLPDEC);
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putreg32(pllsetup->pllmdec, LPC54_SYSCON_SYSPLLMDEC);
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putreg32(pllsetup->pllmdec | SYSCON_SYSPLLMDEC_MREQ,
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LPC54_SYSCON_SYSPLLMDEC);
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/* Flags for lock or power on */
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if ((pllsetup->pllflags & (PLL_SETUPFLAG_POWERUP | PLL_SETUPFLAG_WAITLOCK)) != 0)
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{
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/* If turning the PLL back on, perform the following sequence to
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* accelerate PLL lock.
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*/
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volatile uint32_t delay;
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2017-12-10 15:54:24 +01:00
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uint32_t maxcco = (1 << 18) | 0x5dd2; /* CCO = 1.6Ghz + MDEC enabled */
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2017-12-07 20:30:02 +01:00
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uint32_t ssctrl = getreg32(LPC54_SYSCON_SYSPLLMDEC) & ~SYSCON_SYSPLLMDEC_MREQ;
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/* Initialize and power up PLL */
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putreg32(maxcco, LPC54_SYSCON_SYSPLLMDEC);
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2017-12-15 00:29:15 +01:00
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lpc54_syspll_powerup();
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2017-12-07 20:30:02 +01:00
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/* Set MREQ to activate */
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putreg32(maxcco | SYSCON_SYSPLLMDEC_MREQ, LPC54_SYSCON_SYSPLLMDEC);
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/* Delay for 72 uSec @ 12Mhz */
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for (delay = 0; delay < 172; delay++)
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{
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}
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/* Clear MREQ to prepare for restoring MREQ */
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putreg32(ssctrl, LPC54_SYSCON_SYSPLLMDEC);
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/* set original value back and activate */
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putreg32(ssctrl | SYSCON_SYSPLLMDEC_MREQ, LPC54_SYSCON_SYSPLLMDEC);
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/* Enable PLL */
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2017-12-15 00:29:15 +01:00
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lpc54_syspll_powerup();
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2017-12-07 20:30:02 +01:00
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}
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/* Wait for the lock? */
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if ((pllsetup->pllflags & PLL_SETUPFLAG_WAITLOCK) != 0)
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{
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while ((getreg32(LPC54_SYSCON_SYSPLLSTAT) & SYSCON_SYSPLLSTAT_LOCK) == 0)
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{
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}
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}
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}
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: lpc54_clockconfig
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*
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* Description:
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* Called to initialize the LPC54628. This does whatever setup is needed
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* to put the MCU in a usable state. This includes the initialization of
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* clocking using the settings in board.h. This function also performs
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* other low-level chip as necessary.
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*
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*****************************************************************************/
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void lpc54_clockconfig(FAR const struct pll_setup_s *pllsetup)
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{
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/* Set up the clock sources */
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/* Power up the FRO 12MHz clock source */
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2017-12-15 00:29:15 +01:00
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lpc54_fro_powerup();
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2017-12-07 20:30:02 +01:00
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/* Switch to FRO 12MHz first to ensure we can change voltage without
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* accidentally being below the voltage for current speed.
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*/
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putreg32(SYSCON_MAINCLKSELA_FRO12, LPC54_SYSCON_MAINCLKSELA);
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putreg32(SYSCON_MAINCLKSELB_MAINCLKSELA, LPC54_SYSCON_MAINCLKSELB);
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/* Set the voltage for the find PLL output frequency. This assumes
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* that the PLL output frequncy is >=12MHz.
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*/
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lpc54_setvoltage(pllsetup->pllfout);
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/* Set up the FLASH wait states for the core
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*
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* REVISIT: Should this be the PLL output frequency (Main clock) or
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* the AHB clock?
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*/
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lpc54_set_flash_waitstates(pllsetup->pllfout);
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/* Set up the PLL clock source to FRO 12MHz */
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putreg32(pllsetup->pllclksel, LPC54_SYSCON_SYSPLLCLKSEL);
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/* Configure the PLL */
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lpc54_configure_pll(pllsetup);
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/* Set up the AHB/CPU clock divider */
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putreg32(pllsetup->ahbdiv, LPC54_SYSCON_AHBCLKDIV);
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/* Switch System clock to SYS PLL */
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putreg32(SYSCON_MAINCLKSELB_PLLCLK, LPC54_SYSCON_MAINCLKSELB);
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putreg32(SYSCON_MAINCLKSELA_FRO12, LPC54_SYSCON_MAINCLKSELA);
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}
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