2017-10-09 21:06:47 +02:00
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/****************************************************************************
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* arch/arm/include/bcm2708/irq.h
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*
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* Copyright (C) 2017 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/* This file should never be included directed but, rather, only indirectly through
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* nuttx/irq.h
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*/
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#ifndef __ARCH_ARM_INCLUDE_BCM2708_IRQ_H
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#define __ARCH_ARM_INCLUDE_BCM2708_IRQ_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <arch/bcm2708/chip.h>
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Chip-Specific External interrupts */
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#if defined(CONFIG_ARCH_CHIP_BCM2835)
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/* Interrupt decode algorithm:
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*
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* 1) Check bits 0 through BPR_BIT_LAST in the basic pending register. For
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* each bit set, dispatch IRQ = bit number
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* 2) If bits set in pending register 1, check bits IPR1_BIT_FIRST through
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* IPR1_BIT_LAST for the pending 1 register. For each bit set, dispatch
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* IRQ = bit number + IPR1_IRQ_FIRST - IPR1_BIT_FIRST.
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* 2) If bits set in pending register 2, check bits IPR2_BIT_FIRST through
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* IPR2_BIT_LAST for the pending 2 register. For each bit set, dispatch
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* IRQ = bit number + IPR2_IRQ_FIRST - IPR2_BIT_FIRST.
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*/
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/* Basic pending register */
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#define BPR_IRQ_FIRST 0 /* IRQ of first defined bit */
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#define BPR_BIT_FIRST 0 /* First defined bit */
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2017-10-17 22:53:11 +02:00
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#define BCM_IRQ_ARM_TIMER (BPR_IRQ_FIRST + 0) /* Bit 0: ARM Timer IRQ pending */
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#define BCM_IRQ_ARM_MAILBOX (BPR_IRQ_FIRST + 1) /* Bit 1: ARM Mailbox IRQ pending */
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#define BCM_IRQ_ARM_DOORBELL_0 (BPR_IRQ_FIRST + 2) /* Bit 2: ARM Doorbell 0 IRQ pending */
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#define BCM_IRQ_ARM_DOORBELL_1 (BPR_IRQ_FIRST + 3) /* Bit 3: ARM Doorbell 2 IRQ pending */
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#define BCM_IRQ_VPU0_HALTED (BPR_IRQ_FIRST + 4) /* Bit 4: GPU0 halted IRQ pending
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* (Or GPU1 halted if bit 10 of control
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* register 1 is set) */
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#define BCM_IRQ_VPU1_HALTED (BPR_IRQ_FIRST + 5) /* Bit 5: GPU1 halted IRQ pending */
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#define BCM_IRQ_ILLEGAL_TYPE0 (BPR_IRQ_FIRST + 6) /* Bit 6: Illegal access type 1 IRQ pending */
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#define BCM_IRQ_ILLEGAL_TYPE1 (BPR_IRQ_FIRST + 7) /* Bit 7: Illegal access type 0 IRQ pending */
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#define BCM_IRQ_PENDING1 (BPR_IRQ_FIRST + 8) /* Bit 8: Bits set in pending register 1 */
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#define BCM_IRQ_PENDING2 (BPR_IRQ_FIRST + 9) /* Bit 9: Bits set in pending register 2 */
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#define BCM_IRQ_JPEG (BPR_IRQ_FIRST + 10) /* Bit 10: GPU IRQ 7 */
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#define BCM_IRQ_USB (BPR_IRQ_FIRST + 11) /* Bit 11: GPU IRQ 9 */
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#define BCM_IRQ_3D (BPR_IRQ_FIRST + 12) /* Bit 12: GPU IRQ 10 */
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#define BCM_IRQ_DMA2 (BPR_IRQ_FIRST + 13) /* Bit 13: GPU IRQ 18 */
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#define BCM_IRQ_DMA3 (BPR_IRQ_FIRST + 14) /* Bit 14: GPU IRQ 19 */
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#define BCM_IRQ_I2C (BPR_IRQ_FIRST + 15) /* Bit 15: GPU IRQ 53 */
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#define BCM_IRQ_SPI (BPR_IRQ_FIRST + 16) /* Bit 16: GPU IRQ 54 */
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#define BCM_IRQ_I2SPCM (BPR_IRQ_FIRST + 17) /* Bit 17: GPU IRQ 55 */
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#define BCM_IRQ_SDIO (BPR_IRQ_FIRST + 18) /* Bit 18: GPU IRQ 56 */
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#define BCM_IRQ_UART (BPR_IRQ_FIRST + 19) /* Bit 19: GPU IRQ 57 */
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#define BCM_IRQ_ARASANSDIO (BPR_IRQ_FIRST + 20) /* Bit 20: GPU IRQ 61 */
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2017-10-09 21:06:47 +02:00
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#define BPR_BIT_IRQMASK 0x001ffcff /* Mask of defined interrupts */
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2017-10-17 22:53:11 +02:00
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#define BPR_BIT_LAST BCM_IRQ_ARASANSDIO /* IRQ of last defined bit */
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2017-10-09 21:06:47 +02:00
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#define BPR_IRQ_LAST 20 /* Last defined bit */
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/* IRQ pending 1 register */
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#define IPR1_IRQ_FIRST (BPR_IRQ_LAST + 1) /* IRQ of first defined bit */
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2017-10-17 22:53:11 +02:00
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#define IPR1_BIT_FIRST (0) /* First defined bit */
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#define BCM_IRQ_TIMER0 (IPR1_IRQ_FIRST + 0) /* Bit 0: System Timer Compare Register 0 */
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#define BCM_IRQ_TIMER1 (IPR1_IRQ_FIRST + 1) /* Bit 1: System Timer Compare Register 1 */
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#define BCM_IRQ_TIMER2 (IPR1_IRQ_FIRST + 2) /* Bit 2: System Timer Compare Register 2 */
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#define BCM_IRQ_TIMER3 (IPR1_IRQ_FIRST + 3) /* Bit 3: System Timer Compare Register 3 */
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#define BCM_IRQ_CODEC0 (IPR1_IRQ_FIRST + 4)
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#define BCM_IRQ_CODEC1 (IPR1_IRQ_FIRST + 5)
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#define BCM_IRQ_CODEC2 (IPR1_IRQ_FIRST + 6)
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#define BCM_IRQ_VC_JPEG (IPR1_IRQ_FIRST + 7)
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#define BCM_IRQ_ISP (IPR1_IRQ_FIRST + 8)
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#define BCM_IRQ_VC_USB (IPR1_IRQ_FIRST + 9) /* Bit 9: USB Controller */
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#define BCM_IRQ_VC_3D (IPR1_IRQ_FIRST + 10)
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#define BCM_IRQ_TRANSPOSER (IPR1_IRQ_FIRST + 11)
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#define BCM_IRQ_MULTICORESYNC0 (IPR1_IRQ_FIRST + 12)
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#define BCM_IRQ_MULTICORESYNC1 (IPR1_IRQ_FIRST + 13)
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#define BCM_IRQ_MULTICORESYNC2 (IPR1_IRQ_FIRST + 14)
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#define BCM_IRQ_MULTICORESYNC3 (IPR1_IRQ_FIRST + 15)
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#define BCM_IRQ_DMA0 (IPR1_IRQ_FIRST + 16)
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#define BCM_IRQ_DMA1 (IPR1_IRQ_FIRST + 17)
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#define BCM_IRQ_VC_DMA2 (IPR1_IRQ_FIRST + 18)
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#define BCM_IRQ_VC_DMA3 (IPR1_IRQ_FIRST + 19)
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#define BCM_IRQ_DMA4 (IPR1_IRQ_FIRST + 20)
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#define BCM_IRQ_DMA5 (IPR1_IRQ_FIRST + 21)
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#define BCM_IRQ_DMA6 (IPR1_IRQ_FIRST + 22)
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#define BCM_IRQ_DMA7 (IPR1_IRQ_FIRST + 23)
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#define BCM_IRQ_DMA8 (IPR1_IRQ_FIRST + 24)
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#define BCM_IRQ_DMA9 (IPR1_IRQ_FIRST + 25)
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#define BCM_IRQ_DMA10 (IPR1_IRQ_FIRST + 26)
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#define BCM_IRQ_DMA11 (IPR1_IRQ_FIRST + 27)
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#define BCM_IRQ_DMA12 (IPR1_IRQ_FIRST + 28)
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#define BCM_IRQ_AUX (IPR1_IRQ_FIRST + 29) /* Bit 29: Aux interrupt */
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#define BCM_IRQ_ARM (IPR1_IRQ_FIRST + 30)
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#define BCM_IRQ_VPUDMA (IPR1_IRQ_FIRST + 31)
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2017-10-09 21:06:47 +02:00
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#define IPR1_BIT_IRQMASK 0x20000000 /* Mask of defined interrupts */
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2017-10-17 22:53:11 +02:00
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#define IPR1_IRQ_LAST BCM_IRQ_VPUDMA /* IRQ of last defined bit */
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#define IPR1_BIT_LAST (31) /* Last defined bit */
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2017-10-09 21:06:47 +02:00
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/* IRQ pending 1 register */
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#define IPR2_IRQ_FIRST (IPR1_IRQ_LAST + 1) /* IRQ of first defined bit */
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2017-10-17 22:53:11 +02:00
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#define IPR2_BIT_FIRST (0) /* First defined bit */
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#define BCM_IRQ_HOSTPORT (IPR2_IRQ_FIRST + 0)
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#define BCM_IRQ_VIDEOSCALER (IPR2_IRQ_FIRST + 1)
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#define BCM_IRQ_CCP2TX (IPR2_IRQ_FIRST + 2)
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#define BCM_IRQ_SDC (IPR2_IRQ_FIRST + 3)
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#define BCM_IRQ_DSI0 (IPR2_IRQ_FIRST + 4)
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#define BCM_IRQ_AVE (IPR2_IRQ_FIRST + 5)
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#define BCM_IRQ_CAM0 (IPR2_IRQ_FIRST + 6)
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#define BCM_IRQ_CAM1 (IPR2_IRQ_FIRST + 7)
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#define BCM_IRQ_HDMI0 (IPR2_IRQ_FIRST + 8)
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#define BCM_IRQ_HDMI1 (IPR2_IRQ_FIRST + 9)
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#define BCM_IRQ_PIXELVALVE1 (IPR2_IRQ_FIRST + 10)
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#define BCM_IRQ_I2CSPISLV (IPR2_IRQ_FIRST + 11) /* Bit 11: I2C/SPI slave */
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#define BCM_IRQ_DSI1 (IPR2_IRQ_FIRST + 12)
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#define BCM_IRQ_PWA0 (IPR2_IRQ_FIRST + 13) /* Bit 13: PWA0 */
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#define BCM_IRQ_PWA1 (IPR2_IRQ_FIRST + 14) /* Bit 14: PWA1 */
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#define BCM_IRQ_CPR (IPR2_IRQ_FIRST + 15)
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#define BCM_IRQ_SMI (IPR2_IRQ_FIRST + 16) /* Bit 16: SMI */
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#define BCM_IRQ_GPIO0 (IPR2_IRQ_FIRST + 17) /* Bit 17: GPIO interrupt 0 */
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#define BCM_IRQ_GPIO1 (IPR2_IRQ_FIRST + 18) /* Bit 18: GPIO interrupt 1 */
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#define BCM_IRQ_GPIO2 (IPR2_IRQ_FIRST + 19) /* Bit 19: GPIO interrupt 2 */
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#define BCM_IRQ_GPIO3 (IPR2_IRQ_FIRST + 20) /* Bit 20: GPIO interrupt 3 */
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#define BCM_IRQ_VC_I2C (IPR2_IRQ_FIRST + 21) /* Bit 21: I2C interrupt */
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#define BCM_IRQ_VC_SPI (IPR2_IRQ_FIRST + 22) /* Bit 22: SPI interrupt */
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#define BCM_IRQ_VC_I2SPCM (IPR2_IRQ_FIRST + 23) /* Bit 23: PCM audio interrupt */
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#define BCM_IRQ_VC_SDIO (IPR2_IRQ_FIRST + 24) /* Bit 24: SDIO interrupt */
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#define BCM_IRQ_VC_UART (IPR2_IRQ_FIRST + 25)
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#define BCM_IRQ_SLIMBUS (IPR2_IRQ_FIRST + 26)
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#define BCM_IRQ_VEC (IPR2_IRQ_FIRST + 27)
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#define BCM_IRQ_CPG (IPR2_IRQ_FIRST + 28)
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#define BCM_IRQ_RNG (IPR2_IRQ_FIRST + 29)
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#define BCM_IRQ_VC_ARASANSDIO (IPR2_IRQ_FIRST + 30) /* Bit 30: SD Host Controller */
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#define BCM_IRQ_AVSPMON (IPR2_IRQ_FIRST + 31)
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#define IPR2_BIT_IRQMASK 0xffffffff /* Mask of defined interrupts */
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#define IPR2_IRQ_LAST BCM_IRQ_AVSPMON /* IRQ of last defined bit */
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#define IPR2_BIT_LAST (31) /* Last defined bit */
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/* Number of interrupts */
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2017-10-17 15:37:44 +02:00
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#define NR_INTERRUPTS (IPR2_IRQ_LAST + 1)
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/* Second level GPIO interrupts */
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#ifdef CONFIG_BCM2708_GPIO_IRQ
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2017-10-18 18:13:10 +02:00
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# define BCM_IRQ_GPIO(n) (NR_INTERRUPTS + (n)) /* IRQ number of pin n */
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# define BCM_IRQ_GPIO0_FIRST (NR_INTERRUPTS) /* IRQ number of first GPIO0 interrupt */
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# define BCM_IRQ_GPIO1_FIRST (NR_INTERRUPTS + 32) /* IRQ number of first GPIO1 interrupt */
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2017-10-17 15:37:44 +02:00
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# define NR_GPIOINTS (54)
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#else
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# define NR_GPIOINTS (0)
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#endif
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/* Number of supported IRQs */
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#define NR_IRQS (NR_INTERRUPTS + NR_GPIOINTS)
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2017-10-09 21:06:47 +02:00
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#else
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# error Unrecognized BCM2708 chip
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#endif
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/****************************************************************************
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* Public Types
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****************************************************************************/
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#ifndef __ASSEMBLY__
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/****************************************************************************
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* Public Data
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****************************************************************************/
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif
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#endif /* __ARCH_ARM_INCLUDE_BCM2708_IRQ_H */
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