2016-12-04 14:23:31 +01:00
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/****************************************************************************
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* arch/arm/src/sam34/sam4cm_cpustart.c
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*
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2021-03-15 00:20:50 +01:00
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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2016-12-04 14:23:31 +01:00
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*
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2021-03-15 00:20:50 +01:00
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* http://www.apache.org/licenses/LICENSE-2.0
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2016-12-04 14:23:31 +01:00
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*
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2021-03-15 00:20:50 +01:00
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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2016-12-04 14:23:31 +01:00
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <assert.h>
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#include <debug.h>
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#include <string.h>
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#include <stdio.h>
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2016-12-10 00:10:59 +01:00
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#include <errno.h>
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2016-12-04 14:23:31 +01:00
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#include <nuttx/arch.h>
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#include <nuttx/spinlock.h>
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2016-12-07 16:08:20 +01:00
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#include <nuttx/sched_note.h>
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2016-12-04 14:23:31 +01:00
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#include "nvic.h"
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2020-05-01 03:20:29 +02:00
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#include "arm_arch.h"
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2016-12-04 14:23:31 +01:00
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#include "sched/sched.h"
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#include "init/init.h"
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2020-05-01 03:20:29 +02:00
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#include "arm_internal.h"
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2019-05-25 15:37:39 +02:00
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#include "hardware/sam_pmc.h"
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#include "hardware/sam_rstc.h"
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#include "hardware/sam4cm_ipc.h"
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2016-12-04 14:23:31 +01:00
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#include "sam4cm_periphclks.h"
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#ifdef CONFIG_SMP
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#if 0
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# define DPRINTF(fmt, args...) _err(fmt, ##args)
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#else
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# define DPRINTF(fmt, args...) do {} while (0)
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#endif
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2019-10-16 05:16:48 +02:00
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#define CPU1_VECTOR_ISTACK (SAM_INTSRAM1_BASE)
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#define CPU1_VECTOR_RESETV (SAM_INTSRAM1_BASE + 4)
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2016-12-04 14:23:31 +01:00
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/****************************************************************************
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* Public Data
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****************************************************************************/
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volatile static spinlock_t g_cpu1_boot;
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2017-02-27 13:27:56 +01:00
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extern int arm_pause_handler(int irq, void *c, FAR void *arg);
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2016-12-04 14:23:31 +01:00
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2020-07-21 20:21:47 +02:00
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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2016-12-04 14:23:31 +01:00
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/****************************************************************************
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* Name: cpu1_boot
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*
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* Description:
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* This is the boot vector for CM4P1
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*
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* Input Parameters:
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*
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* Returned Value:
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*
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****************************************************************************/
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static void cpu1_boot(void)
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{
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int cpu;
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/* Disable CMCC1 */
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putreg32(0, 0x48018008);
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while ((getreg32(0x4801800c) & 0x01) != 0);
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cpu = up_cpu_index();
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DPRINTF("cpu = %d\n", cpu);
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if (cpu == 1)
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{
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/* Use CPU0 vectors */
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putreg32((uint32_t)&_stext, NVIC_VECTAB);
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sam_ipc1_enableclk();
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/* Clear : write-only */
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putreg32(0x1, SAM_IPC1_ICCR);
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/* Enable : write-only */
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putreg32(0x1, SAM_IPC1_IECR);
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2017-02-27 13:27:56 +01:00
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irq_attach(SAM_IRQ_IPC1, arm_pause_handler, NULL);
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2016-12-04 14:23:31 +01:00
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up_enable_irq(SAM_IRQ_IPC1);
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}
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spin_unlock(&g_cpu1_boot);
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2016-12-07 16:08:20 +01:00
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#ifdef CONFIG_SCHED_INSTRUMENTATION
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/* Notify that this CPU has started */
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sched_note_cpu_started(this_task());
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#endif
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2016-12-04 14:23:31 +01:00
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/* Then transfer control to the IDLE task */
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2020-07-21 20:21:47 +02:00
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nx_idle_trampoline();
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2016-12-04 14:23:31 +01:00
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}
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/****************************************************************************
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* Name: up_cpu_start
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*
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* Description:
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* In an SMP configution, only one CPU is initially active (CPU 0). System
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* initialization occurs on that single thread. At the completion of the
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* initialization of the OS, just before beginning normal multitasking,
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* the additional CPUs would be started by calling this function.
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*
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* Each CPU is provided the entry point to is IDLE task when started. A
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* TCB for each CPU's IDLE task has been initialized and placed in the
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2020-02-23 09:50:23 +01:00
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* CPU's g_assignedtasks[cpu] list. Not stack has been allocated or
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2016-12-04 14:23:31 +01:00
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* initialized.
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*
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* The OS initialization logic calls this function repeatedly until each
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* CPU has been started, 1 through (CONFIG_SMP_NCPUS-1).
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*
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* Input Parameters:
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* cpu - The index of the CPU being started. This will be a numeric
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* value in the range of from one to (CONFIG_SMP_NCPUS-1). (CPU
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* 0 is already active)
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*
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* Returned Value:
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* Zero on success; a negated errno value on failure.
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*
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****************************************************************************/
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int up_cpu_start(int cpu)
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{
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struct tcb_s *tcb = current_task(cpu);
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2020-07-21 20:21:47 +02:00
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DPRINTF("cpu=%d\n", cpu);
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2016-12-04 14:23:31 +01:00
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if (cpu != 1)
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2016-12-07 16:08:20 +01:00
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{
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return -EINVAL;
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}
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#ifdef CONFIG_SCHED_INSTRUMENTATION
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/* Notify of the start event */
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sched_note_cpu_start(this_task(), cpu);
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#endif
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2016-12-04 14:23:31 +01:00
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/* Reset coprocessor */
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putreg32(0x5a000000, SAM_RSTC_CPMR);
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/* Enable Coprocessor Bus Master Clock (write-only) */
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putreg32(PMC_CPKEY | PMC_CPBMCK, SAM_PMC_SCER);
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/* Enable Coprocessor Clock (write-only) */
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putreg32(PMC_CPKEY | PMC_CPCK, SAM_PMC_SCER);
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/* Set Coprocessor Clock Prescalar */
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modifyreg32(SAM_PMC_MCKR, PMC_MCKR_CPPRES_MASK, 0);
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/* Set Coprocessor Clock Source */
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modifyreg32(SAM_PMC_MCKR, PMC_MCKR_CPCSS_MASK, PMC_MCKR_CPCSS_PLLB);
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/* Unreset coprocessor pheripheral */
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putreg32(0x5a000010, SAM_RSTC_CPMR);
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/* Enable clock for SRAM1 where CPU1 starts (write-only) */
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putreg32(PMC_PID42, SAM_PMC_PCER1);
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/* Clear SRAM1 */
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memset((void *)SAM_INTSRAM1_BASE, 0, 16 * 1024);
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/* Copy initial vectors for CPU1 */
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2021-04-12 17:44:08 +02:00
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putreg32((uint32_t)tcb->stack_base_ptr +
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tcb->adj_stack_size, CPU1_VECTOR_ISTACK);
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2019-10-16 05:16:48 +02:00
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putreg32((uint32_t)cpu1_boot, CPU1_VECTOR_RESETV);
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2016-12-04 14:23:31 +01:00
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spin_lock(&g_cpu1_boot);
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/* Unreset coprocessor */
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putreg32(0x5a000011, SAM_RSTC_CPMR);
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/* IRQ setup CPU1->CPU0 */
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sam_ipc0_enableclk();
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putreg32(0x1, SAM_IPC0_ICCR); /* clear : write-only */
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putreg32(0x1, SAM_IPC0_IECR); /* enable : write-only */
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2017-02-27 13:27:56 +01:00
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irq_attach(SAM_IRQ_IPC0, arm_pause_handler, NULL);
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2016-12-04 14:23:31 +01:00
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up_enable_irq(SAM_IRQ_IPC0);
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2017-06-28 21:16:48 +02:00
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2016-12-04 14:23:31 +01:00
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spin_lock(&g_cpu1_boot);
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/* CPU1 boot done */
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spin_unlock(&g_cpu1_boot);
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return 0;
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}
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#endif /* CONFIG_SMP */
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