283 lines
11 KiB
C
283 lines
11 KiB
C
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/****************************************************************************************************
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* configs/cloudctrl/src/cloudctrl-internal.h
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* arch/arm/src/board/cloudctrl-internal.n
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*
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* Copyright (C) 2012 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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* Darcy Gong <darcy.gong@gmail.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************************************/
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#ifndef __CONFIGS_CLOUDCTRLL_SRC_CLOUDCTRL_INTERNAL_H
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#define __CONFIGS_CLOUDCTRLL_SRC_CLOUDCTRL_INTERNAL_H
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/****************************************************************************************************
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* Included Files
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****************************************************************************************************/
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#include <nuttx/config.h>
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#include <nuttx/compiler.h>
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#include <stdint.h>
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/****************************************************************************************************
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* Definitions
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****************************************************************************************************/
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/* Configuration ************************************************************************************/
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/* How many SPI modules does this chip support? */
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#if STM32_NSPI < 1
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# undef CONFIG_STM32_SPI1
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# undef CONFIG_STM32_SPI2
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# undef CONFIG_STM32_SPI3
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#elif STM32_NSPI < 2
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# undef CONFIG_STM32_SPI2
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# undef CONFIG_STM32_SPI3
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#elif STM32_NSPI < 3
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# undef CONFIG_STM32_SPI3
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#endif
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/* cloudctrl GPIO Configuration **********************************************************************/
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/* STM3240G-EVAL GPIOs ******************************************************************************/
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/* Ethernet
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*
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* -- ---- -------------- ----------------------------------------------------------
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* PN NAME SIGNAL NOTES
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* -- ---- -------------- ----------------------------------------------------------
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* 24 PA1 MII_RX_CLK Ethernet PHY NOTE: Despite the MII labeling of these
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* RMII_REF_CLK Ethernet PHY signals, the DM916AEP is actually configured
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* 25 PA2 MII_MDIO Ethernet PHY to work in RMII mode.
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* 48 PB11 MII_TX_EN Ethernet PHY
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* 51 PB12 MII_TXD0 Ethernet PHY
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* 52 PB13 MII_TXD1 Ethernet PHY
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* 16 PC1 MII_MDC Ethernet PHY
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* 34 PC5 MII_INT Ethernet PHY
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* 55 PD8 MII_RX_DV Ethernet PHY. Requires CONFIG_STM32_ETH_REMAP
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* 55 PD8 RMII_CRSDV Ethernet PHY. Requires CONFIG_STM32_ETH_REMAP
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* 56 PD9 MII_RXD0 Ethernet PHY. Requires CONFIG_STM32_ETH_REMAP
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* 57 PD10 MII_RXD1 Ethernet PHY. Requires CONFIG_STM32_ETH_REMAP
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*
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* The board desdign can support a 50MHz external clock to drive the PHY
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* (U9). However, on my board, U9 is not present.
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*
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* 67 PA8 MCO DM9161AEP
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*/
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#ifdef CONFIG_STM32_ETHMAC
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# define GPIO_MII_INT (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_EXTI|GPIO_PORTC|GPIO_PIN5)
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#endif
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/* Use MCU Pin Reset DM9161 PHY Chip */
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#ifdef CONFIG_PHY_DM9161
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# define GPIO_DM9161_RET (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|GPIO_OUTPUT_SET|\
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GPIO_PORTB|GPIO_PIN15)
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#endif
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/* Wireless
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*
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* -- ---- -------------- -------------------------------------------------------------------
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* PN NAME SIGNAL NOTES
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* -- ---- -------------- -------------------------------------------------------------------
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* 26 PA3 315M_VT
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* 17 PC2 WIRELESS_INT
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* 18 PC3 WIRELESS_CE To the NRF24L01 2.4G wireless module
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* 59 PD12 WIRELESS_CS To the NRF24L01 2.4G wireless module
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*/
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#define GPIO_WIRELESS_CS (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\
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GPIO_OUTPUT_SET|GPIO_PORTD|GPIO_PIN12)
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/* Buttons
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*
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* -- ---- -------------- -------------------------------------------------------------------
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* PN NAME SIGNAL NOTES
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* -- ---- -------------- -------------------------------------------------------------------
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* 23 PA0 WAKEUP Connected to KEY3. Active low: Closing KEY4 pulls WAKEUP to ground.
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* 47 PB10 USERKEY Connected to KEY1
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* 33 PC4 TAMPER Connected to KEY2
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*/
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/* BUTTONS -- NOTE that all have EXTI interrupts configured */
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#define MIN_IRQBUTTON BUTTON_KEY1
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#define MAX_IRQBUTTON BUTTON_KEY3
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#define NUM_IRQBUTTONS (BUTTON_KEY3 - BUTTON_KEY1 + 1)
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#define GPIO_BTN_WAKEUP (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_EXTI|GPIO_PORTC|GPIO_PIN4)
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#define GPIO_BTN_USERKEY (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_EXTI|GPIO_PORTB|GPIO_PIN10)
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#define GPIO_BTN_TAMPER (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_EXTI|GPIO_PORTA|GPIO_PIN0)
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/* LEDs
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*
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* -- ---- -------------- -------------------------------------------------------------------
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* PN NAME SIGNAL NOTES
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* -- ---- -------------- -------------------------------------------------------------------
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* 1 PE2 LED1 Active low: Pulled high
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* 2 PE3 LED2 Active low: Pulled high
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* 3 PE4 LED3 Active low: Pulled high
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* 4 PE5 LED4 Active low: Pulled high
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*/
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#define GPIO_LED1 (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\
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GPIO_OUTPUT_SET|GPIO_PORTE|GPIO_PIN2)
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#define GPIO_LED2 (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\
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GPIO_OUTPUT_SET|GPIO_PORTE|GPIO_PIN3)
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#define GPIO_LED3 (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\
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GPIO_OUTPUT_SET|GPIO_PORTE|GPIO_PIN4)
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#define GPIO_LED4 (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\
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GPIO_OUTPUT_SET|GPIO_PORTE|GPIO_PIN5)
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/* RS-485
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*
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* -- ---- -------------- -------------------------------------------------------------------
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* PN NAME SIGNAL NOTES
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* -- ---- -------------- -------------------------------------------------------------------
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* 88 PD7 485_DIR SP3485 read enable (not)
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*/
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/* To be provided */
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/* USB
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*
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* -- ---- -------------- -------------------------------------------------------------------
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* PN NAME SIGNAL NOTES
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* -- ---- -------------- -------------------------------------------------------------------
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* 95 PB8 USB_PWR Drives USB VBUS
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*/
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#define GPIO_OTGFS_PWRON (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_SPEED_100MHz|\
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GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8)
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/* Audio DAC
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*
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* -- ---- -------------- -------------------------------------------------------------------
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* PN NAME SIGNAL NOTES
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* -- ---- -------------- -------------------------------------------------------------------
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*/
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/* To be provided */
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/* SPI FLASH
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*
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* -- ---- -------------- -------------------------------------------------------------------
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* PN NAME SIGNAL NOTES
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* -- ---- -------------- -------------------------------------------------------------------
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* 96 PB9 F_CS To both the TFT LCD (CN13) and to the W25X16 SPI FLASH
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*/
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#define GPIO_FLASH_CS (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\
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GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN9)
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/* Relays */
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#define NUM_RELAYS 2
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#define GPIO_RELAYS_R00 (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\
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GPIO_OUTPUT_SET|GPIO_PORTE|GPIO_PIN0)
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#define GPIO_RELAYS_R01 (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\
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GPIO_OUTPUT_SET|GPIO_PORTE|GPIO_PIN1)
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/****************************************************************************************************
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* Public Types
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****************************************************************************************************/
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/****************************************************************************************************
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* Public data
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****************************************************************************************************/
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#ifndef __ASSEMBLY__
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/****************************************************************************************************
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* Public Functions
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****************************************************************************************************/
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/****************************************************************************************************
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* Name: stm32_spiinitialize
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*
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* Description:
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* Called to configure SPI chip select GPIO pins for the STM3240G-EVAL board.
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*
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****************************************************************************************************/
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void weak_function stm32_spiinitialize(void);
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/****************************************************************************************************
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* Name: stm32_usbinitialize
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*
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* Description:
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* Called from stm32_usbinitialize very early in inialization to setup USB-related GPIO pins for
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* the STM3240G-EVAL board.
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*
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****************************************************************************************************/
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#ifdef CONFIG_STM32_OTGFS
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void weak_function stm32_usbinitialize(void);
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#endif
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/****************************************************************************************************
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* Name: stm32_usbhost_initialize
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*
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* Description:
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* Called at application startup time to initialize the USB host functionality. This function will
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* start a thread that will monitor for device connection/disconnection events.
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*
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****************************************************************************************************/
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#if defined(CONFIG_STM32_OTGFS) && defined(CONFIG_USBHOST)
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int stm32_usbhost_initialize(void);
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#endif
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/****************************************************************************
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* Name: stm32_sdinitialize
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*
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* Description:
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* Initialize the SPI-based SD card. Requires CONFIG_DISABLE_MOUNTPOINT=n
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* and CONFIG_STM32_SPI1=y
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*
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****************************************************************************/
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int stm32_sdinitialize(int minor);
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/****************************************************************************
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* Name: stm32_w25initialize
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*
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* Description:
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* Initialize and register the W25 FLASH file system.
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*
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****************************************************************************/
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#ifdef CONFIG_MTD_W25
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int stm32_w25initialize(int minor);
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __CONFIGS_CLOUDCTRLL_SRC_CLOUDCTRL_INTERNAL_H */
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