2013-07-30 03:57:15 +02:00
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/****************************************************************************
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* arch/arm/src/armv7-a/cp15_invalidate_dcache_all.S
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*
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* Copyright (C) 2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* References:
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*
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* "Cortex-A5<EFBFBD> MPCore, Technical Reference Manual", Revision: r0p1,
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* Copyright <EFBFBD> 2010 ARM. All rights reserved. ARM DDI 0434B (ID101810)
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* "ARM<EFBFBD> Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
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* Copyright <EFBFBD> 1996-1998, 2000, 2004-2012 ARM. All rights reserved. ARM
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* DDI 0406C.b (ID072512)
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*
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* Portions of this file derive from Atmel sample code for the SAMA5D3 Cortex-A5
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* which also has a modified BSD-style license:
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*
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* Copyright (c) 2012, Atmel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor Atmel nor the names of the contributors may
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* be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include "cp15.h"
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.file "cp15_invalidate_dcache_all.S"
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/****************************************************************************
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* Preprocessor Definitions
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****************************************************************************/
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/****************************************************************************
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* Public Symbols
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****************************************************************************/
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.globl cp15_invalidate_dcache_all
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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.text
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/****************************************************************************
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* Name: cp15_invalidate_dcache_all
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*
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* Description:
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* Invalidate the entire contents of D cache.
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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.globl cp15_invalidate_dcache_all
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.type cp15_invalidate_dcache_all, function
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cp15_invalidate_dcache_all:
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mrc CP15_CCSIDR(r0) /* Read the Cache Size Identification Register */
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ldr r3, =0xffff /* Isolate the NumSets field (bits 13-27) */
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and r0, r3, r0, lsr #13 /* r0=NumSets (number of sets - 1) */
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mov r1, #0 /* r1 = way loop counter */
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way_loop:
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2013-09-22 16:54:06 +02:00
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2013-07-30 03:57:15 +02:00
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mov r3, #0 /* r3 = set loop counter */
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set_loop:
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mov r2, r1, lsl #30 /* r2 = way loop counter << 30 */
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orr r2, r3, lsl #5 /* r2 = set/way cache operation format */
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mcr CP15_DCISW(r2) /* Data Cache Invalidate by Set/Way */
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add r3, r3, #1 /* Increment set counter */
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cmp r0, r3 /* Last set? */
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bne set_loop /* Keep looping if not */
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2013-09-22 16:54:06 +02:00
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2013-07-30 03:57:15 +02:00
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add r1, r1, #1 /* Increment the way counter */
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cmp r1, #4 /* Last way? (four ways assumed) */
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bne way_loop /* Keep looping if not */
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dsb
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bx lr
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.size cp15_invalidate_dcache_all, . - cp15_invalidate_dcache_all
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.end
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