348 lines
12 KiB
C
348 lines
12 KiB
C
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/****************************************************************************
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* arch/arm/src/stm32wl5/stm32wl5_lowputc.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <arch/board/board.h>
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#include "arm_internal.h"
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#include "arm_internal.h"
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#include "chip.h"
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#include "stm32wl5.h"
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#include "stm32wl5_rcc.h"
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#include "stm32wl5_gpio.h"
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#include "stm32wl5_uart.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Select USART parameters for the selected console */
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#ifdef HAVE_CONSOLE
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# if defined(CONFIG_LPUART1_SERIAL_CONSOLE)
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# define STM32WL5_CONSOLE_BASE STM32WL5_LPUART1_BASE
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# define STM32WL5_APBCLOCK STM32WL5_PCLK1_FREQUENCY
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# define STM32WL5_CONSOLE_APBREG STM32WL5_RCC_APB1ENR2
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# define STM32WL5_CONSOLE_APBEN RCC_APB1ENR2_LPUART1EN
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# define STM32WL5_CONSOLE_BAUD CONFIG_LPUART1_BAUD
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# define STM32WL5_CONSOLE_BITS CONFIG_LPUART1_BITS
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# define STM32WL5_CONSOLE_PARITY CONFIG_LPUART1_PARITY
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# define STM32WL5_CONSOLE_2STOP CONFIG_LPUART1_2STOP
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# define STM32WL5_CONSOLE_TX GPIO_LPUART1_TX
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# define STM32WL5_CONSOLE_RX GPIO_LPUART1_RX
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# ifdef CONFIG_LPUART1_RS485
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# define STM32WL5_CONSOLE_RS485_DIR GPIO_LPUART1_RS485_DIR
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# if (CONFIG_LPUART1_RS485_DIR_POLARITY == 0)
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# define STM32WL5_CONSOLE_RS485_DIR_POLARITY false
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# else
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# define STM32WL5_CONSOLE_RS485_DIR_POLARITY true
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# endif
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# endif
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# elif defined(CONFIG_USART1_SERIAL_CONSOLE)
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# define STM32WL5_CONSOLE_BASE STM32WL5_USART1_BASE
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# define STM32WL5_APBCLOCK STM32WL5_PCLK2_FREQUENCY
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# define STM32WL5_CONSOLE_APBREG STM32WL5_RCC_APB2ENR
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# define STM32WL5_CONSOLE_APBEN RCC_APB2ENR_USART1EN
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# define STM32WL5_CONSOLE_BAUD CONFIG_USART1_BAUD
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# define STM32WL5_CONSOLE_BITS CONFIG_USART1_BITS
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# define STM32WL5_CONSOLE_PARITY CONFIG_USART1_PARITY
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# define STM32WL5_CONSOLE_2STOP CONFIG_USART1_2STOP
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# define STM32WL5_CONSOLE_TX GPIO_USART1_TX
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# define STM32WL5_CONSOLE_RX GPIO_USART1_RX
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# ifdef CONFIG_USART1_RS485
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# define STM32WL5_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR
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# if (CONFIG_USART1_RS485_DIR_POLARITY == 0)
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# define STM32WL5_CONSOLE_RS485_DIR_POLARITY false
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# else
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# define STM32WL5_CONSOLE_RS485_DIR_POLARITY true
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# endif
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# endif
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# elif defined(CONFIG_USART2_SERIAL_CONSOLE)
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# define STM32WL5_CONSOLE_BASE STM32WL5_USART2_BASE
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# define STM32WL5_APBCLOCK STM32WL5_PCLK1_FREQUENCY
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# define STM32WL5_CONSOLE_APBREG STM32WL5_RCC_APB1ENR1
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# define STM32WL5_CONSOLE_APBEN RCC_APB1ENR1_USART2EN
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# define STM32WL5_CONSOLE_BAUD CONFIG_USART2_BAUD
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# define STM32WL5_CONSOLE_BITS CONFIG_USART2_BITS
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# define STM32WL5_CONSOLE_PARITY CONFIG_USART2_PARITY
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# define STM32WL5_CONSOLE_2STOP CONFIG_USART2_2STOP
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# define STM32WL5_CONSOLE_TX GPIO_USART2_TX
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# define STM32WL5_CONSOLE_RX GPIO_USART2_RX
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# ifdef CONFIG_USART2_RS485
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# define STM32WL5_CONSOLE_RS485_DIR GPIO_USART2_RS485_DIR
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# if (CONFIG_USART2_RS485_DIR_POLARITY == 0)
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# define STM32WL5_CONSOLE_RS485_DIR_POLARITY false
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# else
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# define STM32WL5_CONSOLE_RS485_DIR_POLARITY true
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# endif
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# endif
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# endif
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/* CR1 settings */
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# if STM32WL5_CONSOLE_BITS == 9
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# define USART_CR1_M0_VALUE USART_CR1_M0
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# define USART_CR1_M1_VALUE 0
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# elif STM32WL5_CONSOLE_BITS == 7
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# define USART_CR1_M0_VALUE 0
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# define USART_CR1_M1_VALUE USART_CR1_M1
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# else /* 8 bits */
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# define USART_CR1_M0_VALUE 0
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# define USART_CR1_M1_VALUE 0
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# endif
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# if STM32WL5_CONSOLE_PARITY == 1 /* odd parity */
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# define USART_CR1_PARITY_VALUE (USART_CR1_PCE|USART_CR1_PS)
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# elif STM32WL5_CONSOLE_PARITY == 2 /* even parity */
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# define USART_CR1_PARITY_VALUE USART_CR1_PCE
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# else /* no parity */
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# define USART_CR1_PARITY_VALUE 0
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# endif
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# define USART_CR1_CLRBITS \
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(USART_CR1_UE | USART_CR1_UESM | USART_CR1_RE | USART_CR1_TE | USART_CR1_PS | \
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USART_CR1_PCE | USART_CR1_WAKE | USART_CR1_M0 | USART_CR1_M1 | \
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USART_CR1_MME | USART_CR1_OVER8 | USART_CR1_DEDT_MASK | \
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USART_CR1_DEAT_MASK | USART_CR1_ALLINTS)
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# define USART_CR1_SETBITS (USART_CR1_M0_VALUE|USART_CR1_M1_VALUE|USART_CR1_PARITY_VALUE)
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/* CR2 settings */
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# if STM32WL5_CONSOLE_2STOP != 0
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# define USART_CR2_STOP2_VALUE USART_CR2_STOP2
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# else
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# define USART_CR2_STOP2_VALUE 0
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# endif
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# define USART_CR2_CLRBITS \
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(USART_CR2_ADDM7 | USART_CR2_LBDL | USART_CR2_LBDIE | USART_CR2_LBCL | \
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USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | USART_CR2_STOP_MASK | \
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USART_CR2_LINEN | USART_CR2_SWAP | USART_CR2_RXINV | USART_CR2_TXINV | \
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USART_CR2_DATAINV | USART_CR2_MSBFIRST | USART_CR2_ABREN | \
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USART_CR2_ABRMOD_MASK | USART_CR2_RTOEN | USART_CR2_ADD_MASK)
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# define USART_CR2_SETBITS USART_CR2_STOP2_VALUE
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/* CR3 settings */
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# define USART_CR3_CLRBITS \
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(USART_CR3_EIE | USART_CR3_IREN | USART_CR3_IRLP | USART_CR3_HDSEL | \
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USART_CR3_NACK | USART_CR3_SCEN | USART_CR3_DMAR | USART_CR3_DMAT | \
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USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_CTSIE | USART_CR3_ONEBIT | \
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USART_CR3_OVRDIS | USART_CR3_DDRE | USART_CR3_DEM | USART_CR3_DEP | \
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USART_CR3_SCARCNT2_MASK | USART_CR3_WUS_MASK | USART_CR3_WUFIE)
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# define USART_CR3_SETBITS 0
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# undef USE_OVER8
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/* Calculate USART BAUD rate divider */
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/* Baud rate for standard USART (SPI mode included):
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*
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* In case of oversampling by 16, the equation is:
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* baud = fCK / UARTDIV
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* UARTDIV = fCK / baud
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*
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* In case of oversampling by 8, the equation is:
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*
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* baud = 2 * fCK / UARTDIV
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* UARTDIV = 2 * fCK / baud
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*/
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# define STM32WL5_USARTDIV8 \
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(((STM32WL5_APBCLOCK << 1) + (STM32WL5_CONSOLE_BAUD >> 1)) / STM32WL5_CONSOLE_BAUD)
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# define STM32WL5_USARTDIV16 \
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((STM32WL5_APBCLOCK + (STM32WL5_CONSOLE_BAUD >> 1)) / STM32WL5_CONSOLE_BAUD)
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/* Use oversamply by 8 only if the divisor is small. But what is small? */
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# if defined(CONFIG_LPUART1_SERIAL_CONSOLE)
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/* lpuart has different formula for baud rate than normal uart */
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# define STM32WL5_BRR_VALUE \
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(((256ull * STM32WL5_APBCLOCK) / STM32WL5_CONSOLE_BAUD) & LPUART_BRR_MASK)
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# else /* CONFIG_LPUART1_SERIAL_CONSOLE */
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# if STM32WL5_USARTDIV8 > 2000
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# define STM32WL5_BRR_VALUE STM32WL5_USARTDIV16
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# else
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# define USE_OVER8 1
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# define STM32WL5_BRR_VALUE \
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((STM32WL5_USARTDIV8 & 0xfff0) | ((STM32WL5_USARTDIV8 & 0x000f) >> 1))
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# endif
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# endif /* CONFIG_LPUART1_SERIAL_CONSOLE */
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#endif /* HAVE_CONSOLE */
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/****************************************************************************
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* Private Types
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****************************************************************************/
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/****************************************************************************
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* Private Function Prototypes
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****************************************************************************/
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/****************************************************************************
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* Private Variables
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****************************************************************************/
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: arm_lowputc
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*
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* Description:
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* Output one byte on the serial console
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*
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****************************************************************************/
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void arm_lowputc(char ch)
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{
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#ifdef HAVE_CONSOLE
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/* Wait until the TX data register is empty */
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while ((getreg32(STM32WL5_CONSOLE_BASE + STM32WL5_USART_ISR_OFFSET) &
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USART_ISR_TXE) == 0);
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#ifdef STM32WL5_CONSOLE_RS485_DIR
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stm32wl5_gpiowrite(STM32WL5_CONSOLE_RS485_DIR,
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STM32WL5_CONSOLE_RS485_DIR_POLARITY);
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#endif
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/* Then send the character */
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putreg32((uint32_t)ch, STM32WL5_CONSOLE_BASE + STM32WL5_USART_TDR_OFFSET);
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#ifdef STM32WL5_CONSOLE_RS485_DIR
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while ((getreg32(STM32WL5_CONSOLE_BASE + STM32WL5_USART_ISR_OFFSET) &
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USART_ISR_TC) == 0);
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stm32wl5_gpiowrite(STM32WL5_CONSOLE_RS485_DIR,
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!STM32WL5_CONSOLE_RS485_DIR_POLARITY);
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#endif
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#endif /* HAVE_CONSOLE */
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}
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/****************************************************************************
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* Name: stm32wl5_lowsetup
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*
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* Description:
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* This performs basic initialization of the USART used for the serial
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* console. Its purpose is to get the console output available as soon
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* as possible.
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*
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****************************************************************************/
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void stm32wl5_lowsetup(void)
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{
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#if defined(HAVE_UART)
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#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
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uint32_t cr;
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#endif
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#if defined(HAVE_CONSOLE)
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/* Enable USART APB1/2 clock */
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modifyreg32(STM32WL5_CONSOLE_APBREG, 0, STM32WL5_CONSOLE_APBEN);
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#endif
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/* Enable the console USART and configure GPIO pins needed for rx/tx.
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*
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* NOTE: Clocking for selected U[S]ARTs was already provided in
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* stm32wl5_rcc.c
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*/
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#ifdef STM32WL5_CONSOLE_TX
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stm32wl5_configgpio(STM32WL5_CONSOLE_TX);
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#endif
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#ifdef STM32WL5_CONSOLE_RX
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stm32wl5_configgpio(STM32WL5_CONSOLE_RX);
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#endif
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#ifdef STM32WL5_CONSOLE_RS485_DIR
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stm32wl5_configgpio(STM32WL5_CONSOLE_RS485_DIR);
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stm32wl5_gpiowrite(STM32WL5_CONSOLE_RS485_DIR,
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!STM32WL5_CONSOLE_RS485_DIR_POLARITY);
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#endif
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/* Enable and configure the selected console device */
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#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
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/* Configure CR2 */
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cr = getreg32(STM32WL5_CONSOLE_BASE + STM32WL5_USART_CR2_OFFSET);
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cr &= ~USART_CR2_CLRBITS;
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cr |= USART_CR2_SETBITS;
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putreg32(cr, STM32WL5_CONSOLE_BASE + STM32WL5_USART_CR2_OFFSET);
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/* Configure CR1 */
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cr = getreg32(STM32WL5_CONSOLE_BASE + STM32WL5_USART_CR1_OFFSET);
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cr &= ~USART_CR1_CLRBITS;
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cr |= USART_CR1_SETBITS;
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putreg32(cr, STM32WL5_CONSOLE_BASE + STM32WL5_USART_CR1_OFFSET);
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/* Configure CR3 */
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cr = getreg32(STM32WL5_CONSOLE_BASE + STM32WL5_USART_CR3_OFFSET);
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cr &= ~USART_CR3_CLRBITS;
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cr |= USART_CR3_SETBITS;
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putreg32(cr, STM32WL5_CONSOLE_BASE + STM32WL5_USART_CR3_OFFSET);
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|
|
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||
|
|
/* Configure the USART Baud Rate */
|
||
|
|
|
||
|
|
putreg32(STM32WL5_BRR_VALUE,
|
||
|
|
STM32WL5_CONSOLE_BASE + STM32WL5_USART_BRR_OFFSET);
|
||
|
|
|
||
|
|
/* Select oversampling by 8 */
|
||
|
|
|
||
|
|
cr = getreg32(STM32WL5_CONSOLE_BASE + STM32WL5_USART_CR1_OFFSET);
|
||
|
|
#ifdef USE_OVER8
|
||
|
|
cr |= USART_CR1_OVER8;
|
||
|
|
putreg32(cr, STM32WL5_CONSOLE_BASE + STM32WL5_USART_CR1_OFFSET);
|
||
|
|
#endif
|
||
|
|
|
||
|
|
/* Enable Rx, Tx, and the USART */
|
||
|
|
|
||
|
|
cr |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE);
|
||
|
|
putreg32(cr, STM32WL5_CONSOLE_BASE + STM32WL5_USART_CR1_OFFSET);
|
||
|
|
|
||
|
|
#endif /* HAVE_CONSOLE && !CONFIG_SUPPRESS_UART_CONFIG */
|
||
|
|
#endif /* HAVE_UART */
|
||
|
|
}
|