2021-03-21 11:37:01 +01:00
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/****************************************************************************
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2019-08-12 20:10:54 +02:00
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* arch/arm/include/s32k1xx/s32k14x_irq.h
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*
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2021-03-20 21:46:19 +01:00
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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2019-08-12 20:10:54 +02:00
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*
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2021-03-20 21:46:19 +01:00
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* http://www.apache.org/licenses/LICENSE-2.0
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2019-08-12 20:10:54 +02:00
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*
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2021-03-20 21:46:19 +01:00
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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2019-08-12 20:10:54 +02:00
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*
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2021-03-21 11:37:01 +01:00
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****************************************************************************/
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2019-08-12 20:10:54 +02:00
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2021-03-21 11:37:01 +01:00
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/* This file should never be included directly but, rather,
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* only indirectly through nuttx/irq.h
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2019-08-12 20:10:54 +02:00
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*/
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#ifndef __ARCH_ARM_INCLUDE_S32K1XX_S32K14XX_IRQ_H
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#define __ARCH_ARM_INCLUDE_S32K1XX_S32K14XX_IRQ_H
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2021-03-21 11:37:01 +01:00
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/****************************************************************************
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2019-08-12 20:10:54 +02:00
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* Included Files
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2021-03-21 11:37:01 +01:00
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****************************************************************************/
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2019-08-12 20:10:54 +02:00
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#include <nuttx/config.h>
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2021-03-21 11:37:01 +01:00
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/****************************************************************************
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* Pre-processor Prototypes
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****************************************************************************/
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2019-08-12 20:10:54 +02:00
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2021-03-21 11:37:01 +01:00
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/* IRQ numbers.
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* The IRQ number corresponds vector number and hence map directly to
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* bits in the NVIC. This does, however, waste several words of memory in
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* the IRQ to handle mapping tables.
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2019-08-12 20:10:54 +02:00
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*/
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/* Processor Exceptions (vectors 0-15) */
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2019-08-14 20:40:51 +02:00
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#define S32K1XX_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
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/* Vector 0: Reset stack pointer value */
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/* Vector 1: Reset (not handler as an IRQ) */
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#define S32K1XX_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
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#define S32K1XX_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
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#define S32K1XX_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */
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#define S32K1XX_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */
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#define S32K1XX_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */
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#define S32K1XX_IRQ_SVCALL (11) /* Vector 11: SVC call */
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#define S32K1XX_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */
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/* Vector 13: Reserved */
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#define S32K1XX_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
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#define S32K1XX_IRQ_SYSTICK (15) /* Vector 15: System tick */
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/* External interrupts (vectors >= 16).
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* These definitions are chip-specific
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*/
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2019-08-12 20:10:54 +02:00
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2019-08-14 20:40:51 +02:00
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#define S32K1XX_IRQ_INTERRUPT (16) /* Vector number of the first external interrupt */
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#define S32K1XX_IRQ_DMACH0 (16) /* DMA channel 0 transfer complete */
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#define S32K1XX_IRQ_DMACH1 (17) /* DMA channel 1 transfer complete */
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#define S32K1XX_IRQ_DMACH2 (18) /* DMA channel 2 transfer complete */
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#define S32K1XX_IRQ_DMACH3 (19) /* DMA channel 3 transfer complete */
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#define S32K1XX_IRQ_DMACH4 (20) /* DMA channel 4 transfer complete */
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#define S32K1XX_IRQ_DMACH5 (21) /* DMA channel 5 transfer complete */
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#define S32K1XX_IRQ_DMACH6 (22) /* DMA channel 6 transfer complete */
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#define S32K1XX_IRQ_DMACH7 (23) /* DMA channel 7 transfer complete */
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#define S32K1XX_IRQ_DMACH8 (24) /* DMA channel 8 transfer complete */
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#define S32K1XX_IRQ_DMACH9 (25) /* DMA channel 9 transfer complete */
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#define S32K1XX_IRQ_DMACH10 (26) /* DMA channel 10 transfer complete */
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#define S32K1XX_IRQ_DMACH11 (27) /* DMA channel 11 transfer complete */
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#define S32K1XX_IRQ_DMACH12 (28) /* DMA channel 12 transfer complete */
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#define S32K1XX_IRQ_DMACH13 (29) /* DMA channel 13 transfer complete */
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#define S32K1XX_IRQ_DMACH14 (30) /* DMA channel 14 transfer complete */
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#define S32K1XX_IRQ_DMACH15 (31) /* DMA channel 15 transfer complete */
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#define S32K1XX_IRQ_DMACH_ERR (32) /* DMA error interrupt channels 0-15 */
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#define S32K1XX_IRQ_MCM (33) /* FPU sources */
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#define S32K1XX_IRQ_FTFCCMD (34) /* FTFC command complete */
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#define S32K1XX_IRQ_FTFCCOL (35) /* FTFC read collition */
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#define S32K1XX_IRQ_PMC (36) /* PMC Low voltage detect interrupt */
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#define S32K1XX_IRQ_FTFCDBL (37) /* FTFC Double bit */
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#define S32K1XX_IRQ_WDOG (38) /* WDOG interrupt request out before wdg reset out */
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#define S32K1XX_IRQ_EWM (38) /* EWM output as interrupt */
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#define S32K1XX_IRQ_RCM (39) /* RCM Asynchronous Interrupt */
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#define S32K1XX_IRQ_LPI2C0M (40) /* LPI2C Master Interrupt */
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#define S32K1XX_IRQ_LPI2C0S (41) /* LPI2C Slave Interrupt */
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#define S32K1XX_IRQ_LPSPI0 (42) /* LPSPI0 Interrupt */
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#define S32K1XX_IRQ_LPSPI1 (43) /* LPSPI1 Interrupt */
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#define S32K1XX_IRQ_LPSPI2 (44) /* LPSPI2 Interrupt */
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#define S32K1XX_IRQ_LPI2C1M (45) /* LPI21 Master Interrupt */
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#define S32K1XX_IRQ_LPI2C1S (46) /* LPI21 Slave Interrupt */
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#define S32K1XX_IRQ_LPUART0 (47) /* LPUART0 Interrupt */
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/* Reserved (48) */
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#define S32K1XX_IRQ_LPUART1 (49) /* LPUART1 Interrupt */
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/* Reserved (50) */
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#define S32K1XX_IRQ_LPUART2 (51) /* LPUART0 Interrupt */
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/* Reserved (52-54) */
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#define S32K1XX_IRQ_ADC0 (55) /* ADC0 Interrupt */
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#define S32K1XX_IRQ_ADC1 (56) /* ADC1 Interrupt */
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#define S32K1XX_IRQ_CMP0 (57) /* CMP0 Interrupt */
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/* Reserved (58-59) */
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#define S32K1XX_IRQ_ERMS (60) /* ERM single bit error correction */
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#define S32K1XX_IRQ_ERMD (61) /* ERM double bit error non-correctable */
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#define S32K1XX_IRQ_RTC_ALARM (62) /* RTC alarm interrupt */
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#define S32K1XX_IRQ_RTC_SEC (63) /* RTC seconds interrupt */
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#define S32K1XX_IRQ_LPIT0 (64) /* LPIT interrupt */
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#define S32K1XX_IRQ_LPIT1 (65) /* LPIT interrupt */
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#define S32K1XX_IRQ_LPIT2 (66) /* LPIT interrupt */
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#define S32K1XX_IRQ_LPIT3 (67) /* LPIT interrupt */
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#define S32K1XX_IRQ_PDB0 (68) /* PDB0 interrupt */
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/* Reserved (69-70) */
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#define S32K1XX_IRQ_SAI1TX (71) /* SAI1 Transmit Synchronous Interrupt */
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#define S32K1XX_IRQ_SAI1RX (72) /* SAI1 Receive Synchronous Interrupt */
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#define S32K1XX_IRQ_SCGBUS (73) /* SCG bus interrupt request */
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#define S32K1XX_IRQ_LPTIMER (74) /* LPTIMER interrupt request */
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#define S32K1XX_IRQ_PORTA (75) /* PORTA Interrupt */
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#define S32K1XX_IRQ_PORTB (76) /* PORTB Interrupt */
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#define S32K1XX_IRQ_PORTC (77) /* PORTC Interrupt */
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#define S32K1XX_IRQ_PORTD (78) /* PORTD Interrupt */
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#define S32K1XX_IRQ_PORTE (79) /* PORTE Interrupt */
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#define S32K1XX_IRQ_SOFTWARE (80) /* Software Interrupt */
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#define S32K1XX_IRQ_QUADSPI (81) /* QuadSPI Interrupts */
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/* Reserved (82-83) */
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#define S32K1XX_IRQ_PDB1 (84) /* PDB1 Interrupt */
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#define S32K1XX_IRQ_FLEXIO (85) /* FlexIO Interrupt */
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#define S32K1XX_IRQ_SAI0_TX (86) /* SAI0 Transmit Synchronous Interrupt */
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#define S32K1XX_IRQ_SAI0_RX (87) /* SAI0 Receive Synchronous Interrupt */
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#define S32K1XX_IRQ_ENET_TIMER (88) /* ENET 1588 timer, time stamp, etc. */
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#define S32K1XX_IRQ_ENET_TXDONE (89) /* ENET Data Tx Transfer Done Interrupt */
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#define S32K1XX_IRQ_ENET_RXDONE (90) /* ENET Data Rx Transfer Done Interrupt */
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#define S32K1XX_IRQ_ENET_ERROR (91) /* ENET Error Interrupt */
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#define S32K1XX_IRQ_ENET_STOP (92) /* ENET Graceful Stop Interrupt */
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#define S32K1XX_IRQ_ENET_WAKE (93) /* ENET Wake from Sleep Interrupt */
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#define S32K1XX_IRQ_CAN0_BUS (94) /* CAN0 Bus On/Off Tx/Rx Warning */
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#define S32K1XX_IRQ_CAN0_ERROR (95) /* CAN0 Bus Error Interrupt */
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#define S32K1XX_IRQ_CAN0_LPRX (96) /* CAN0 Message Rx/Timeout in low power mode */
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#define S32K1XX_IRQ_CAN0_0_15 (97) /* CAN0 OR'ed Message buffer (0-15) */
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#define S32K1XX_IRQ_CAN0_16_31 (98) /* CAN0 OR'ed Message buffer (16-31) */
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/* Reserved (99-100) */
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#define S32K1XX_IRQ_CAN1_BUS (101) /* CAN1 Bus On/Off Tx/Rx Warning */
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#define S32K1XX_IRQ_CAN1_ERROR (102) /* CAN1 Bus Error Interrupt */
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/* Reserved (103) */
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#define S32K1XX_IRQ_CAN1_0_15 (104) /* CAN1 OR'ed Message buffer (0-15) */
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#define S32K1XX_IRQ_CAN1_16_31 (105) /* CAN1 OR'ed Message buffer (16-31) */
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/* Reserved (106-107) */
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#define S32K1XX_IRQ_CAN2_BUS (108) /* CAN2 Bus On/Off Tx/Rx Warning */
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#define S32K1XX_IRQ_CAN2_ERROR (109) /* CAN2 Bus Error Interrupt */
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/* Reserved (110) */
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#define S32K1XX_IRQ_CAN2_0_15 (111) /* CAN2 OR'ed Message buffer (0-15) */
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#define S32K1XX_IRQ_CAN2_16_31 (112) /* CAN2 OR'ed Message buffer (16-31) */
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/* Reserved (113-114) */
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#define S32K1XX_IRQ_FTM0_CH0_1 (115) /* FTM0 Channel 0/1 Interrupt */
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#define S32K1XX_IRQ_FTM0_CH2_3 (116) /* FTM0 Channel 2/3 Interrupt */
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#define S32K1XX_IRQ_FTM0_CH4_5 (117) /* FTM0 Channel 4/5 Interrupt */
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#define S32K1XX_IRQ_FTM0_CH6_7 (118) /* FTM0 Channel 6/7 Interrupt */
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#define S32K1XX_IRQ_FTM0_FAULT (119) /* FTM0 Fault Interrupt */
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#define S32K1XX_IRQ_FTM0_OVERFLOW (120) /* FTM0 Counter Overflow/Reload Interrupt */
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#define S32K1XX_IRQ_FTM1_CH0_1 (121) /* FTM1 Channel 0/1 Interrupt */
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#define S32K1XX_IRQ_FTM1_CH2_2 (122) /* FTM1 Channel 2/3 Interrupt */
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#define S32K1XX_IRQ_FTM1_CH4_5 (123) /* FTM1 Channel 4/5 Interrupt */
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#define S32K1XX_IRQ_FTM1_CH6_7 (124) /* FTM1 Channel 6/7 Interrupt */
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#define S32K1XX_IRQ_FTM1_FAULT (125) /* FTM1 Fault Interrupt */
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#define S32K1XX_IRQ_FTM1_OVERFLOW (126) /* FTM1 Counter Overflow/Reload Interrupt */
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#define S32K1XX_IRQ_FTM2_CH0_1 (127) /* FTM0 Channel 0/1 Interrupt */
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#define S32K1XX_IRQ_FTM2_CH2_2 (128) /* FTM0 Channel 2/3 Interrupt */
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#define S32K1XX_IRQ_FTM2_CH4_5 (129) /* FTM0 Channel 4/5 Interrupt */
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#define S32K1XX_IRQ_FTM2_CH6_7 (130) /* FTM0 Channel 6/7 Interrupt */
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#define S32K1XX_IRQ_FTM2_FAULT (131) /* FTM0 Fault Interrupt */
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#define S32K1XX_IRQ_FTM2_OVERFLOW (132) /* FTM0 Counter Overflow/Reload Interrupt */
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#define S32K1XX_IRQ_FTM3_CH0_1 (133) /* FTM3 Channel 0/1 Interrupt */
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#define S32K1XX_IRQ_FTM3_CH2_2 (134) /* FTM3 Channel 2/3 Interrupt */
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#define S32K1XX_IRQ_FTM3_CH4_5 (135) /* FTM3 Channel 4/5 Interrupt */
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#define S32K1XX_IRQ_FTM3_CH6_7 (136) /* FTM3 Channel 6/7 Interrupt */
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#define S32K1XX_IRQ_FTM3_FAULT (137) /* FTM3 Fault Interrupt */
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#define S32K1XX_IRQ_FTM3_OVERFLOW (138) /* FTM3 Counter Overflow/Reload Interrupt */
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#define S32K1XX_IRQ_FTM4_CH0_1 (139) /* FTM4 Channel 0/1 Interrupt */
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#define S32K1XX_IRQ_FTM4_CH2_2 (140) /* FTM4 Channel 2/3 Interrupt */
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#define S32K1XX_IRQ_FTM4_CH4_5 (141) /* FTM4 Channel 4/5 Interrupt */
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#define S32K1XX_IRQ_FTM4_CH6_7 (142) /* FTM4 Channel 6/7 Interrupt */
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#define S32K1XX_IRQ_FTM4_FAULT (143) /* FTM4 Fault Interrupt */
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#define S32K1XX_IRQ_FTM4_OVERFLOW (144) /* FTM4 Counter Overflow/Reload Interrupt */
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#define S32K1XX_IRQ_FTM5_CH0_1 (145) /* FTM5 Channel 0/1 Interrupt */
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#define S32K1XX_IRQ_FTM5_CH2_2 (146) /* FTM5 Channel 2/3 Interrupt */
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#define S32K1XX_IRQ_FTM5_CH4_5 (147) /* FTM5 Channel 4/5 Interrupt */
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#define S32K1XX_IRQ_FTM5_CH6_7 (148) /* FTM5 Channel 6/7 Interrupt */
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#define S32K1XX_IRQ_FTM5_FAULT (149) /* FTM5 Fault Interrupt */
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#define S32K1XX_IRQ_FTM5_OVERFLOW (150) /* FTM5 Counter Overflow/Reload Interrupt */
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#define S32K1XX_IRQ_FTM6_CH0_1 (151) /* FTM6 Channel 0/1 Interrupt */
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#define S32K1XX_IRQ_FTM6_CH2_2 (152) /* FTM6 Channel 2/3 Interrupt */
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#define S32K1XX_IRQ_FTM6_CH4_5 (153) /* FTM6 Channel 4/5 Interrupt */
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#define S32K1XX_IRQ_FTM6_CH6_7 (154) /* FTM6 Channel 6/7 Interrupt */
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#define S32K1XX_IRQ_FTM6_FAULT (155) /* FTM6 Fault Interrupt */
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#define S32K1XX_IRQ_FTM6_OVERFLOW (156) /* FTM6 Counter Overflow/Reload Interrupt */
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#define S32K1XX_IRQ_FTM7_CH0_1 (157) /* FTM7 Channel 0/1 Interrupt */
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#define S32K1XX_IRQ_FTM7_CH2_2 (158) /* FTM7 Channel 2/3 Interrupt */
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#define S32K1XX_IRQ_FTM7_CH4_5 (159) /* FTM7 Channel 4/5 Interrupt */
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#define S32K1XX_IRQ_FTM7_CH6_7 (160) /* FTM7 Channel 6/7 Interrupt */
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#define S32K1XX_IRQ_FTM7_FAULT (161) /* FTM7 Fault Interrupt */
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#define S32K1XX_IRQ_FTM7_OVERFLOW (162) /* FTM7 Counter Overflow/Reload Interrupt */
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#define S32K1XX_IRQ_NIRQS (163)
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#define S32K1XX_IRQ_NEXTINT (S32K1XX_IRQ_NIRQS - S32K1XX_IRQ_INTERRUPT)
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/* Total number of IRQ numbers */
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2019-08-14 20:40:51 +02:00
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#define NR_IRQS S32K1XX_IRQ_NIRQS
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2019-08-12 20:10:54 +02:00
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#endif /* __ARCH_ARM_INCLUDE_S32K1XX_S32K14XX_IRQ_H */
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