103 lines
2.7 KiB
C
103 lines
2.7 KiB
C
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#ifndef __GENERATED_SDRAM_PHY_H
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#define __GENERATED_SDRAM_PHY_H
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#include <hw/common.h>
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#include <generated/csr.h>
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#include <hw/flags.h>
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#define DFII_NPHASES 4
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static void cdelay(int i);
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static void command_p0(int cmd)
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{
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sdram_dfii_pi0_command_write(cmd);
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sdram_dfii_pi0_command_issue_write(1);
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}
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static void command_p1(int cmd)
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{
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sdram_dfii_pi1_command_write(cmd);
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sdram_dfii_pi1_command_issue_write(1);
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}
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static void command_p2(int cmd)
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{
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sdram_dfii_pi2_command_write(cmd);
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sdram_dfii_pi2_command_issue_write(1);
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}
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static void command_p3(int cmd)
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{
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sdram_dfii_pi3_command_write(cmd);
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sdram_dfii_pi3_command_issue_write(1);
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}
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#define sdram_dfii_pird_address_write(X) sdram_dfii_pi0_address_write(X)
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#define sdram_dfii_piwr_address_write(X) sdram_dfii_pi2_address_write(X)
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#define sdram_dfii_pird_baddress_write(X) sdram_dfii_pi0_baddress_write(X)
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#define sdram_dfii_piwr_baddress_write(X) sdram_dfii_pi2_baddress_write(X)
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#define command_prd(X) command_p0(X)
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#define command_pwr(X) command_p2(X)
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#define DFII_PIX_DATA_SIZE CSR_SDRAM_DFII_PI0_WRDATA_SIZE
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const unsigned int sdram_dfii_pix_wrdata_addr[4] = {
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CSR_SDRAM_DFII_PI0_WRDATA_ADDR,
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CSR_SDRAM_DFII_PI1_WRDATA_ADDR,
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CSR_SDRAM_DFII_PI2_WRDATA_ADDR,
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CSR_SDRAM_DFII_PI3_WRDATA_ADDR
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};
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const unsigned int sdram_dfii_pix_rddata_addr[4] = {
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CSR_SDRAM_DFII_PI0_RDDATA_ADDR,
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CSR_SDRAM_DFII_PI1_RDDATA_ADDR,
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CSR_SDRAM_DFII_PI2_RDDATA_ADDR,
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CSR_SDRAM_DFII_PI3_RDDATA_ADDR
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};
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#define DDR3_MR1 6
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static void init_sequence(void)
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{
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/* Release reset */
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sdram_dfii_pi0_address_write(0x0);
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sdram_dfii_pi0_baddress_write(0);
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sdram_dfii_control_write(DFII_CONTROL_ODT|DFII_CONTROL_RESET_N);
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cdelay(50000);
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/* Bring CKE high */
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sdram_dfii_pi0_address_write(0x0);
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sdram_dfii_pi0_baddress_write(0);
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sdram_dfii_control_write(DFII_CONTROL_CKE|DFII_CONTROL_ODT|DFII_CONTROL_RESET_N);
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cdelay(10000);
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/* Load Mode Register 2 */
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sdram_dfii_pi0_address_write(0x408);
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sdram_dfii_pi0_baddress_write(2);
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command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
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/* Load Mode Register 3 */
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sdram_dfii_pi0_address_write(0x0);
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sdram_dfii_pi0_baddress_write(3);
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command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
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/* Load Mode Register 1 */
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sdram_dfii_pi0_address_write(0x6);
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sdram_dfii_pi0_baddress_write(1);
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command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
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/* Load Mode Register 0, CL=7, BL=8 */
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sdram_dfii_pi0_address_write(0x930);
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sdram_dfii_pi0_baddress_write(0);
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command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
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cdelay(200);
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/* ZQ Calibration */
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sdram_dfii_pi0_address_write(0x400);
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sdram_dfii_pi0_baddress_write(0);
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command_p0(DFII_COMMAND_WE|DFII_COMMAND_CS);
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cdelay(200);
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}
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#endif
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