313 lines
11 KiB
C
313 lines
11 KiB
C
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/***************************************************************************
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* arch/arm/src/cxd56xx/cxd56_audio_bca_reg.h
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*
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* Copyright 2018 Sony Semiconductor Solutions Corporation
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name of Sony Semiconductor Solutions Corporation nor
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* the names of its contributors may be used to endorse or promote
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* products derived from this software without specific prior written
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* permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_CXD56XX_CXD56_AUDIO_BCA_REG_H
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#define __ARCH_ARM_SRC_CXD56XX_CXD56_AUDIO_BCA_REG_H
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/***************************************************************************
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* Included Files
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****************************************************************************/
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#include <arch/chip/audio.h>
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/***************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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typedef enum
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{
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BCA_Mic_In_start_adr,
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BCA_Mic_In_sample_no,
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BCA_Mic_In_rtd_trg,
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BCA_Mic_In_nointr,
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BCA_Mic_In_bitwt,
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BCA_Mic_In_ch8_sel,
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BCA_Mic_In_ch7_sel,
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BCA_Mic_In_ch6_sel,
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BCA_Mic_In_ch5_sel,
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BCA_Mic_In_ch4_sel,
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BCA_Mic_In_ch3_sel,
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BCA_Mic_In_ch2_sel,
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BCA_Mic_In_ch1_sel,
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BCA_Mic_In_start,
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BCA_Mic_In_error_setting,
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BCA_Mic_In_monbuf,
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BCA_I2s1_In_start_adr,
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BCA_I2s1_In_sample_no,
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BCA_I2s1_In_rtd_trg,
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BCA_I2s1_In_nointr,
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BCA_I2s1_In_bitwt,
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BCA_I2s1_In_ch2_sel,
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BCA_I2s1_In_ch1_sel,
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BCA_I2s1_In_Mon_start,
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BCA_I2s1_In_Mon_error_setting,
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BCA_I2s1_In_Mon_monbuf,
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BCA_I2s2_In_start_adr,
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BCA_I2s2_In_sample_no,
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BCA_I2s2_In_rtd_trg,
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BCA_I2s2_In_nointr,
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BCA_I2s2_In_bitwt,
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BCA_I2s2_In_ch2_sel,
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BCA_I2s2_In_ch1_sel,
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BCA_I2s2_In_Mon_start,
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BCA_I2s2_In_Mon_error_setting,
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BCA_I2s2_In_Mon_monbuf,
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BCA_I2s1_Out_start_adr,
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BCA_I2s1_Out_sample_no,
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BCA_I2s1_Out_rtd_trg,
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BCA_I2s1_Out_nointr,
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BCA_I2s1_Out_bitwt,
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BCA_I2s1_Out_sd1_r_sel,
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BCA_I2s1_Out_sd1_l_sel,
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BCA_I2s1_Out_Mon_start,
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BCA_I2s1_Out_Mon_error_setting,
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BCA_I2s1_Out_Mon_monbuf,
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BCA_I2s2_Out_start_adr,
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BCA_I2s2_Out_sample_no,
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BCA_I2s2_Out_rtd_trg,
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BCA_I2s2_Out_nointr,
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BCA_I2s2_Out_bitwt,
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BCA_I2s2_Out_sd1_r_sel,
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BCA_I2s2_Out_sd1_l_sel,
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BCA_I2s2_Out_Mon_start,
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BCA_I2s2_Out_Mon_error_setting,
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BCA_I2s2_Out_Mon_monbuf,
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BCA_I2s_ensel,
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BCA_Mic_In_prdat_u,
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BCA_I2s1_In_prdat_u,
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BCA_I2s2_In_prdat_u,
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BCA_I2s1_Out_prdat_d,
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BCA_I2s2_Out_prdat_d,
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BCA_Mic_Int_Ctrl_done_mic,
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BCA_Mic_Int_Ctrl_err_mic,
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BCA_Mic_Int_Ctrl_smp_mic,
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BCA_Mic_Int_Ctrl_cmb_mic,
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BCA_I2s1_Int_Ctrl_done_i2so,
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BCA_I2s1_Int_Ctrl_err_i2so,
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BCA_I2s1_Int_Ctrl_done_i2si,
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BCA_I2s1_Int_Ctrl_err_i2si,
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BCA_I2s1_Int_Ctrl_smp_i2s,
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BCA_I2s1_Int_Ctrl_cmb_i2s,
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BCA_I2s2_Int_Ctrl_done_i2so,
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BCA_I2s2_Int_Ctrl_err_i2so,
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BCA_I2s2_Int_Ctrl_done_i2si,
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BCA_I2s2_Int_Ctrl_err_i2si,
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BCA_I2s2_Int_Ctrl_smp_i2s,
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BCA_I2s2_Int_Ctrl_cmb_i2s,
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BCA_Mic_Int_Mask_done_mic,
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BCA_Mic_Int_Mask_err_mic,
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BCA_Mic_Int_Mask_smp_mic,
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BCA_Mic_Int_Mask_cmb_mic,
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BCA_Mic_Int_Mask_nostpmsk,
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BCA_Mic_Int_Mask_srst_mic,
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BCA_I2s1_Int_Mask_done_i2so,
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BCA_I2s1_Int_Mask_err_i2so,
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BCA_I2s1_Int_Mask_done_i2si,
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BCA_I2s1_Int_Mask_err_i2si,
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BCA_I2s1_Int_Mask_smp_i2s,
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BCA_I2s1_Int_Mask_cmb_i2s,
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BCA_I2s1_Int_Mask_nostpmsk,
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BCA_I2s1_Int_Mask_srst_i2s,
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BCA_I2s2_Int_Mask_done_i2so,
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BCA_I2s2_Int_Mask_err_i2so,
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BCA_I2s2_Int_Mask_done_i2si,
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BCA_I2s2_Int_Mask_err_i2si,
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BCA_I2s2_Int_Mask_smp_i2s,
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BCA_I2s2_Int_Mask_cmb_i2s,
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BCA_I2s2_Int_Mask_nostpmsk,
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BCA_I2s2_Int_Mask_srst_i2s,
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BCA_Int_m_hresp_err,
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BCA_Int_m_i2s1_bck_err1,
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BCA_Int_m_i2s1_bck_err2,
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BCA_Int_m_anc_faint,
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BCA_Int_m_ovf_smasl,
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BCA_Int_m_ovf_smasr,
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BCA_Int_m_ovf_dnc1l,
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BCA_Int_m_ovf_dnc1r,
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BCA_Int_m_ovf_dnc2l,
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BCA_Int_m_ovf_dnc2r,
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BCA_Int_clr_hresp_err,
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BCA_Int_clr_i2s1_bck_err1,
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BCA_Int_clr_i2S1_bck_err2,
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BCA_Int_clr_anc_faint,
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BCA_Int_clr_ovf_smasl,
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BCA_Int_clr_ovf_smasr,
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BCA_Int_clr_ovf_dnc1l,
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BCA_Int_clr_ovf_dnc1r,
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BCA_Int_clr_ovf_dnc2l,
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BCA_Int_clr_ovf_dnc2r,
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BCA_Int_hresp_err,
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BCA_Int_i2s_bck_err1,
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BCA_Int_i2s_bck_err2,
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BCA_Int_anc_faint,
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BCA_Int_ovf_smasl,
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BCA_Int_ovf_smasr,
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BCA_Int_ovf_dnc1l,
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BCA_Int_ovf_dnc1r,
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BCA_Int_ovf_dnc2l,
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BCA_Int_ovf_dnc2r,
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BCA_Dbg_Mic_ch1_data,
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BCA_Dbg_Mic_ch2_data,
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BCA_Dbg_Mic_ch3_data,
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BCA_Dbg_Mic_ch4_data,
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BCA_Dbg_Mic_ch5_data,
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BCA_Dbg_Mic_ch6_data,
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BCA_Dbg_Mic_ch7_data,
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BCA_Dbg_Mic_ch8_data,
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BCA_Dbg_I2s1_u_ch1_data,
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BCA_Dbg_I2s1_u_ch2_data,
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BCA_Dbg_I2s1_d_ch1_data,
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BCA_Dbg_I2s1_d_ch2_data,
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BCA_Dbg_I2s2_u_ch1_data,
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BCA_Dbg_I2s2_u_ch2_data,
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BCA_Dbg_I2s2_d_ch1_data,
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BCA_Dbg_I2s2_d_ch2_data,
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BCA_Dbg_Ctrl_mic_dbg_en,
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BCA_Dbg_Ctrl_I2s1_dbg_u_en,
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BCA_Dbg_Ctrl_I2s1_dbg_d_en,
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BCA_Dbg_Ctrl_I2s2_dbg_u_en,
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BCA_Dbg_Ctrl_I2s2_dbg_d_en,
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BCA_Clk_En_ahbmstr_mic_en,
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BCA_Clk_En_ahbmstr_I2s1_en,
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BCA_Clk_En_ahbmstr_I2s2_en,
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BCA_Mclk_Mon_thresh,
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AHB_Master_Mic_Mask,
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AHB_Master_I2s1_Mask,
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AHB_Master_I2s2_Mask,
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BCA_REG_MAX_ENTRY
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} BCA_REG_ID;
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#define DMA_STATE_BIT_AC_DONE 1
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#define DMA_STATE_BIT_AC_ERR 2
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#define DMA_STATE_BIT_AC_CMB 8
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#define DMA_STATE_BIT_I2S_OUT_DONE 1
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#define DMA_STATE_BIT_I2S_OUT_ERR 2
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#define DMA_STATE_BIT_I2S_IN_DONE 4
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#define DMA_STATE_BIT_I2S_IN_ERR 8
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#define DMA_STATE_BIT_I2S_CMB 32
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#define DMA_MSTATE_START 1
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#define DMA_MSTART_READY 0
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#define DMA_MSTATE_ERR_OK
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#define DMA_MSTATE_ERR_NO_ENABLE_CH 1
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#define DMA_MSTATE_ERR_CH1_4_INVALID 2
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#define DMA_MSTATE_ERR_CH5_8_INVALID 4
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#define DMA_MSTATE_BUF_EMPTY 3
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#define DMA_CMD_FIFO_NOT_FULL 1
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/***************************************************************************
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* Public Types
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****************************************************************************/
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/***************************************************************************
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* Public Data
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****************************************************************************/
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/***************************************************************************
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* Inline Functions
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****************************************************************************/
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/***************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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void cxd56_audio_bca_reg_clear_bck_err_int(void);
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void cxd56_audio_bca_reg_set_smaster(void);
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void cxd56_audio_bca_reg_set_datarate(uint8_t clk_mode);
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void cxd56_audio_bca_reg_en_fmt24(cxd56_audio_dma_t handle, uint8_t ch_num);
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void cxd56_audio_bca_reg_en_fmt16(cxd56_audio_dma_t handle, uint8_t ch_num);
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void cxd56_audio_bca_reg_en_bus_err_int(void);
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void cxd56_audio_bca_reg_dis_bus_err_int(void);
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void cxd56_audio_bca_reg_get_dma_mstate(cxd56_audio_dma_t handle,
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FAR cxd56_audio_dma_mstate_t *state);
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uint32_t cxd56_audio_bca_reg_get_dma_done_state_mic(void);
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uint32_t cxd56_audio_bca_reg_get_dma_done_state_i2s1(void);
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uint32_t cxd56_audio_bca_reg_get_dma_done_state_i2s2(void);
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void cxd56_audio_bca_reg_mask_done_int(cxd56_audio_dma_t handle);
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void cxd56_audio_bca_reg_unmask_done_int(cxd56_audio_dma_t handle);
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void cxd56_audio_bca_reg_clear_done_int(cxd56_audio_dma_t handle);
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void cxd56_audio_bca_reg_clear_dma_done_state_mic(uint32_t value);
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void cxd56_audio_bca_reg_clear_dma_done_state_i2s1(uint32_t value);
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void cxd56_audio_bca_reg_clear_dma_done_state_i2s2(uint32_t value);
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bool cxd56_audio_bca_reg_is_dma_fifo_empty(cxd56_audio_dma_t handle);
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void cxd56_audio_bca_reg_mask_err_int(cxd56_audio_dma_t handle);
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void cxd56_audio_bca_reg_unmask_err_int(cxd56_audio_dma_t handle);
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void cxd56_audio_bca_reg_clear_err_int(cxd56_audio_dma_t handle);
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void cxd56_audio_bca_reg_mask_cmb_int(cxd56_audio_dma_t handle);
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void cxd56_audio_bca_reg_unmask_cmb_int(cxd56_audio_dma_t handle);
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void cxd56_audio_bca_reg_clear_cmb_int(cxd56_audio_dma_t handle);
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uint32_t cxd56_audio_bca_reg_get_int_status(void);
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void cxd56_audio_bca_reg_clear_int_status(uint32_t int_au);
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void cxd56_audio_bca_reg_mask_bus_int(cxd56_audio_dma_t handle);
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void cxd56_audio_bca_reg_unmask_bus_int(cxd56_audio_dma_t handle);
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void cxd56_audio_bca_reg_set_start_addr(cxd56_audio_dma_t handle,
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uint32_t addr);
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void cxd56_audio_bca_reg_set_sample_no(cxd56_audio_dma_t handle,
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uint32_t sample);
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void cxd56_audio_bca_reg_start_dma(cxd56_audio_dma_t handle,
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bool nointr);
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void cxd56_audio_bca_reg_stop_dma(cxd56_audio_dma_t handle);
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bool cxd56_audio_bca_reg_is_done_int(cxd56_audio_dma_t handle);
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bool cxd56_audio_bca_reg_is_err_int(cxd56_audio_dma_t handle);
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bool cxd56_audio_bca_reg_is_smp_int(cxd56_audio_dma_t handle);
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void cxd56_audio_bca_reg_mask_smp_int(cxd56_audio_dma_t handle);
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void cxd56_audio_bca_reg_unmask_smp_int(cxd56_audio_dma_t handle);
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void cxd56_audio_bca_reg_clear_smp_int(cxd56_audio_dma_t handle);
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uint32_t cxd56_audio_bca_reg_get_mon_state_err(cxd56_audio_dma_t handle);
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uint32_t cxd56_audio_bca_reg_get_mon_state_start(cxd56_audio_dma_t handle);
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uint32_t cxd56_audio_bca_reg_get_mon_state_buf(cxd56_audio_dma_t handle);
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uint32_t cxd56_audio_bca_reg_get_dma_state(cxd56_audio_dma_t handle);
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void cxd56_audio_bca_reg_reset_chsel(cxd56_audio_dma_t handle);
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#endif /* __ARCH_ARM_SRC_CXD56XX_CXD56_AUDIO_BCA_REG_H */
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