94 lines
3.1 KiB
C
94 lines
3.1 KiB
C
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/****************************************************************************
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* boards/risc-v/litex/arty_a7/include/board_memorymap.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __BOARDS_RISCV_LITEX_ARTY_A7_INCLUDE_BOARD_MEMORYMAP_H
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#define __BOARDS_RISCV_LITEX_ARTY_A7_INCLUDE_BOARD_MEMORYMAP_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <stdint.h>
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Kernel code memory (RX) */
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#define KFLASH_START (uintptr_t)__kflash_start
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#define KFLASH_SIZE (uintptr_t)__kflash_size
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#define KSRAM_START (uintptr_t)__ksram_start
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#define KSRAM_SIZE (uintptr_t)__ksram_size
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#define KSRAM_END (uintptr_t)__ksram_end
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/* Kernel RAM (RW) */
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#define PGPOOL_START (uintptr_t)__pgheap_start
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#define PGPOOL_SIZE (uintptr_t)__pgheap_size
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/* Page pool (RWX) */
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#define PGPOOL_START (uintptr_t)__pgheap_start
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#define PGPOOL_SIZE (uintptr_t)__pgheap_size
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#define PGPOOL_END (PGPOOL_START + PGPOOL_SIZE)
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/* User flash */
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#define UFLASH_START (uintptr_t)__uflash_start
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#define UFLASH_SIZE (uintptr_t)__uflash_size
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/* RAMDisk */
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#define RAMDISK_START (uintptr_t)__ramdisk_start
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#define RAMDISK_SIZE (uintptr_t)__ramdisk_size
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/* Kernel code memory (RX) */
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extern uint8_t __kflash_start[];
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extern uint8_t __kflash_size[];
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/* Kernel RAM (RW) */
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extern uint8_t __ksram_start[];
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extern uint8_t __ksram_size[];
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extern uint8_t __ksram_end[];
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/* Page pool (RWX) */
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extern uint8_t __pgheap_start[];
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extern uint8_t __pgheap_size[];
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/* User code memory (RX) */
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extern uint8_t __uflash_start[];
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extern uint8_t __uflash_size[];
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/* ramdisk (RW) */
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extern uint8_t __ramdisk_start[];
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extern uint8_t __ramdisk_size[];
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#endif /* __BOARDS_RISC_V_LITEX_ARTY_A7_INCLUDE_BOARD_MEMORYMAP_H */
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