398 lines
17 KiB
C
398 lines
17 KiB
C
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/* Register Addresses */
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#define MCP2515_RXF0SIDH 0x00
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#define MCP2515_RXF0SIDL 0x01
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#define MCP2515_RXF0EID8 0x02
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#define MCP2515_RXF0EID0 0x03
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#define MCP2515_RXF1SIDH 0x04
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#define MCP2515_RXF1SIDL 0x05
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#define MCP2515_RXF1EID8 0x06
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#define MCP2515_RXF1EID0 0x07
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#define MCP2515_RXF2SIDH 0x08
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#define MCP2515_RXF2SIDL 0x09
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#define MCP2515_RXF2EID8 0x0a
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#define MCP2515_RXF2EID0 0x0b
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#define MCP2515_BFPCTRL 0x0c
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#define MCP2515_TXRTSCTRL 0x0d
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#define MCP2515_CANSTAT 0x0e
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#define MCP2515_CANCTRL 0x0f
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#define MCP2515_RXF3SIDH 0x10
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#define MCP2515_RXF3SIDL 0x11
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#define MCP2515_RXF3EID8 0x12
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#define MCP2515_RXF3EID0 0x13
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#define MCP2515_RXF4SIDH 0x14
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#define MCP2515_RXF4SIDL 0x15
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#define MCP2515_RXF4EID8 0x16
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#define MCP2515_RXF4EID0 0x17
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#define MCP2515_RXF5SIDH 0x18
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#define MCP2515_RXF5SIDL 0x19
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#define MCP2515_RXF5EID8 0x1a
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#define MCP2515_RXF5EID0 0x1b
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#define MCP2515_TEC 0x1c
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#define MCP2515_REC 0x1d
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#define MCP2515_RXM0SIDH 0x20
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#define MCP2515_RXM0SIDL 0x21
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#define MCP2515_RXM0EID8 0x22
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#define MCP2515_RXM0EID0 0x23
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#define MCP2515_RXM1SIDH 0x24
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#define MCP2515_RXM1SIDL 0x25
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#define MCP2515_RXM1EID8 0x26
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#define MCP2515_RXM1EID0 0x27
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#define MCP2515_CNF3 0x28
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#define MCP2515_CNF2 0x29
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#define MCP2515_CNF1 0x2a
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#define MCP2515_CANINTE 0x2b
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#define MCP2515_CANINTF 0x2c
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#define MCP2515_EFLG 0x2d
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#define MCP2515_TXB0CTRL 0x30
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#define MCP2515_TXB0SIDH 0x31
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#define MCP2515_TXB0SIDL 0x32
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#define MCP2515_TXB0EID8 0x33
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#define MCP2515_TXB0EID0 0x34
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#define MCP2515_TXB0DLC 0x35
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#define MCP2515_TXB0D0 0x36
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#define MCP2515_TXB0D1 0x37
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#define MCP2515_TXB0D2 0x38
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#define MCP2515_TXB0D3 0x39
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#define MCP2515_TXB0D4 0x3a
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#define MCP2515_TXB0D5 0x3b
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#define MCP2515_TXB0D6 0x3c
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#define MCP2515_TXB0D7 0x3d
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#define MCP2515_TXB1CTRL 0x40
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#define MCP2515_TXB1SIDH 0x41
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#define MCP2515_TXB1SIDL 0x42
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#define MCP2515_TXB1EID8 0x43
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#define MCP2515_TXB1EID0 0x44
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#define MCP2515_TXB1DLC 0x45
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#define MCP2515_TXB1D0 0x46
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#define MCP2515_TXB1D1 0x47
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#define MCP2515_TXB1D2 0x48
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#define MCP2515_TXB1D3 0x49
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#define MCP2515_TXB1D4 0x4a
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#define MCP2515_TXB1D5 0x4b
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#define MCP2515_TXB1D6 0x4c
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#define MCP2515_TXB1D7 0x4d
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#define MCP2515_TXB2CTRL 0x50
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#define MCP2515_TXB2SIDH 0x51
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#define MCP2515_TXB2SIDL 0x52
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#define MCP2515_TXB2EID8 0x53
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#define MCP2515_TXB2EID0 0x54
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#define MCP2515_TXB2DLC 0x55
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#define MCP2515_TXB2D0 0x56
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#define MCP2515_TXB2D1 0x57
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#define MCP2515_TXB2D2 0x58
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#define MCP2515_TXB2D3 0x59
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#define MCP2515_TXB2D4 0x5a
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#define MCP2515_TXB2D5 0x5b
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#define MCP2515_TXB2D6 0x5c
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#define MCP2515_TXB2D7 0x5d
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#define MCP2515_RXB0CTRL 0x60
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#define MCP2515_RXB0SIDH 0x61
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#define MCP2515_RXB0SIDL 0x62
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#define MCP2515_RXB0EID8 0x63
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#define MCP2515_RXB0EID0 0x64
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#define MCP2515_RXB0DLC 0x65
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#define MCP2515_RXB0D0 0x66
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#define MCP2515_RXB0D1 0x67
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#define MCP2515_RXB0D2 0x68
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#define MCP2515_RXB0D3 0x69
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#define MCP2515_RXB0D4 0x6a
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#define MCP2515_RXB0D5 0x6b
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#define MCP2515_RXB0D6 0x6c
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#define MCP2515_RXB0D7 0x6d
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#define MCP2515_RXB1CTRL 0x70
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#define MCP2515_RXB1SIDH 0x71
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#define MCP2515_RXB1SIDL 0x72
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#define MCP2515_RXB1EID8 0x73
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#define MCP2515_RXB1EID0 0x74
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#define MCP2515_RXB1DLC 0x75
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#define MCP2515_RXB1D0 0x76
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#define MCP2515_RXB1D1 0x77
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#define MCP2515_RXB1D2 0x78
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#define MCP2515_RXB1D3 0x79
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#define MCP2515_RXB1D4 0x7a
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#define MCP2515_RXB1D5 0x7b
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#define MCP2515_RXB1D6 0x7c
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#define MCP2515_RXB1D7 0x7d
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/* Offset to simplify mcp2515_receive() function */
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#define MCP2515_RX0_OFFSET 0x00
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#define MCP2515_RX1_OFFSET 0x10
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/* Offset to simplify mcp2515_send() function */
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#define MCP2515_TX0_OFFSET 0x00
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#define MCP2515_TX1_OFFSET 0x10
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#define MCP2515_TX2_OFFSET 0x20
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/* CANCTRL: CAN CONTROL REGISTER */
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#define CANCTRL_CLKPRE_SHIFT (0) /* Bits 0-1: CLKOUT Pin Prescaler bits */
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#define CANCTRL_CLKPRE_MASK (3 << CANCTRL_CLKPRE_SHIFT)
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#define CANCTRL_CLKEN (1 << 2) /* Bit 2: CLKOUT Pin Enable bit */
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#define CANCTRL_OSM (1 << 3) /* Bit 3: One-Shot Mode bit */
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#define CANCTRL_ABAT (1 << 4) /* Bit 4: Abort All Pending Transmissions bit */
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#define CANCTRL_REQOP_SHIFT (5) /* Bits 5-7: Request Operation Mode bits */
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#define CANCTRL_REQOP_MASK (7 << CANCTRL_REQOP_SHIFT)
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#define CANCTRL_REQOP_NORMAL (0 << CANCTRL_REQOP_SHIFT)
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#define CANCTRL_REQOP_SLEEP (1 << CANCTRL_REQOP_SHIFT)
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#define CANCTRL_REQOP_LOOPBK (2 << CANCTRL_REQOP_SHIFT)
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#define CANCTRL_REQOP_LISTEN (3 << CANCTRL_REQOP_SHIFT)
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#define CANCTRL_REQOP_CONFIG (4 << CANCTRL_REQOP_SHIFT)
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/* TXBnCTRL – TRANSMIT BUFFER n CONTROL REGISTER */
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#define TXBCTRL_TXP_SHIFT (0) /* Bits 0-1: Transmit Buffer Priority */
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#define TXBCTRL_TXP_MASK (3 << MCP2515_TXBCTRL_TXP_SHIFT)
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/* Bit 2: Not used */
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#define TXBCTRL_TXREQ (1 << 3) /* Bit 3: Message Transmit Request bit */
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#define TXBCTRL_TXERR (1 << 4) /* Bit 4: Transmission Error Detected bit */
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#define TXBCTRL_MLOA (1 << 5) /* Bit 5: Message Lost Arbitration bit */
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#define TXBCTRL_ABTF (1 << 6) /* Bit 6: Message Aborted Flag bit */
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/* Bit 7: Not used */
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/* TXRTSCTRL – TXnRTS PIN CONTROL AND STATUS REGISTER */
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#define TXRTSCTRL_B0RTSM (1 << 0) /* Bit 0: TX0RTS Pin mode bit */
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#define TXRTSCTRL_B1RTSM (1 << 1) /* Bit 1: TX1RTS Pin mode bit */
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#define TXRTSCTRL_B2RTSM (1 << 2) /* Bit 2: TX2RTS Pin mode bit */
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#define TXRTSCTRL_B0RTS (1 << 3) /* Bit 3: TX0RTS Pin State bit */
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#define TXRTSCTRL_B1RTS (1 << 4) /* Bit 4: TX1RTS Pin State bit */
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#define TXRTSCTRL_B2RTS (1 << 5) /* Bit 5: TX2RTS Pin State bit */
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/* Bit 6-7: Not used */
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/* TXBnSIDH – TRANSMIT BUFFER n STANDARD IDENTIFIER HIGH */
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#define TXBSIDH_SID_MASK 0xff /* Standard Identifier bits <10:3> */
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/* TXBnSIDL – TRANSMIT BUFFER n STANDARD IDENTIFIER LOW */
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#define TXBSIDL_SID_SHIFT (5) /* Bits 5-7: Standard Identifier bits <2:0> */
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#define TXBSIDL_SID_MASK (0x7 << TXBSIDL_SID_SHIFT)
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#define TXBSIDL_EXIDE (1 << 3) /* Bit 3: Extended Identifier Enable bit */
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#define TXBSIDL_EID_SHIFT (0) /* Bits 0-1: Extended Identifier bits <17:16> */
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#define TXBSIDL_EID_MASK (0x03 << TXBSIDL_EID_MASK)
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/* TXBnEID8 – TRANSMIT BUFFER n EXTENDED IDENTIFIER HIGH */
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#define TXBEID8_EID_MASK 0xff /* Bits 0-7: Extended Identifier bits <15:8> */
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/* TXBnEID0 – TRANSMIT BUFFER n EXTENDED IDENTIFIER LOW */
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#define TXBEID0_EID_MASK 0xff /* Bits 0-7: Extended Identifier bits <7:0> */
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/* TXBnDLC - TRANSMIT BUFFER n DATA LENGTH CODE */
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#define TXBDLC_DLC_SHIFT (0) /* Bits 0-3: Data Length Code <3:0> bits */
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#define TXBDLC_DLC_MASK (0xf << TXBDLC_DLC_SHIFT)
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#define TXBDLC_RTR (1 << 6) /* Bit 6: Remote Transmission Request bit */
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/* TXBnDm – TRANSMIT BUFFER n DATA BYTE m */
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#define TXBD_D0 (1 << 0) /* Bit 0: Transmit Buffer n Data Field Bytes 0 */
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#define TXBD_D1 (1 << 1) /* Bit 1: Transmit Buffer n Data Field Bytes 1 */
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#define TXBD_D2 (1 << 2) /* Bit 2: Transmit Buffer n Data Field Bytes 2 */
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#define TXBD_D3 (1 << 3) /* Bit 3: Transmit Buffer n Data Field Bytes 3 */
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#define TXBD_D4 (1 << 4) /* Bit 4: Transmit Buffer n Data Field Bytes 4 */
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#define TXBD_D5 (1 << 5) /* Bit 5: Transmit Buffer n Data Field Bytes 5 */
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#define TXBD_D6 (1 << 6) /* Bit 6: Transmit Buffer n Data Field Bytes 6 */
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#define TXBD_D7 (1 << 7) /* Bit 7: Transmit Buffer n Data Field Bytes 7 */
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/* RXB0CTRL – RECEIVE BUFFER 0 CONTROL */
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#define RXB0CTRL_FILHIT (1 << 0) /* Bit 0: Filter Hit bit - 1 = Msg was accepted by Filter 1; 0 = Filter 0 */
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#define RXB0CTRL_BUKT1 (1 << 1) /* Bit 1: Read-only Copy of BUKT bit (used internally by the MCP2515) */
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#define RXB0CTRL_BUKT (1 << 2) /* Bit 2: Rollover Enable bit */
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/* These bits are common to RXB0 and RXB1: */
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#define RXBCTRL_RXRTR (1 << 3) /* Bit 3: Received Remote Transfer Request bit */
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/* Bit 4: Not used */
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#define RXBCTRL_RXM_SHIFT (5) /* Bits 5-6: Receive Buffer Operating Mode bits */
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#define RXBCTRL_RXM_MASK (0x3 << RXBCTRL_RXM_SHIFT)
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#define RXBCTRL_RXM_ALLMSG (3 << RXBCTRL_RXM_SHIFT) /* 11: Turn mask/filters off; receive any message */
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#define RXBCTRL_RXM_ALLVALID (0 << RXBCTRL_RXM_SHIFT) /* 00: Receive all valid msgs using (STD or EXT) that meet filter criteria */
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/* Bit 7: Not used */
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/* N.B.: In the datasheet DS21801D the file RXM of RXBnCTRL could to assume
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the value 01 and 10 to receive only STD or EXT msgs respectively.
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But in a more recent datasheet DS20001801H it was removed. */
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/* RXB1CTRL – RECEIVE BUFFER 1 CONTROL */
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#define RXB1CTRL_FILHIT_SHIFT (0) /* Filter Hit bits - indicates which acceptance filter enabled reception of message */
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#define RXB1CTRL_FILHIT_MASK (0x7 << RXB0CTRL_FILHIT_SHIFT)
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#define RXB1CTRL_FILHIT_F5 (5 << RXB1CTRL_FILHIT_SHIFT) /* Acceptance Filter 5 (RXF5) */
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#define RXB1CTRL_FILHIT_F4 (4 << RXB1CTRL_FILHIT_SHIFT) /* Acceptance Filter 4 (RXF4) */
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#define RXB1CTRL_FILHIT_F3 (3 << RXB1CTRL_FILHIT_SHIFT) /* Acceptance Filter 3 (RXF3) */
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#define RXB1CTRL_FILHIT_F2 (2 << RXB1CTRL_FILHIT_SHIFT) /* Acceptance Filter 2 (RXF2) */
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#define RXB1CTRL_FILHIT_F1 (1 << RXB1CTRL_FILHIT_SHIFT) /* Acceptance Filter 1 (RXF1) (Only if BUKT bit set in RXB0CTRL) */
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#define RXB1CTRL_FILHIT_F0 (0 << RXB1CTRL_FILHIT_SHIFT) /* Acceptance Filter 0 (RXF0) (Only if BUKT bit set in RXB0CTRL) */
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/* BFPCTRL – RXnBF PIN CONTROL AND STATUS */
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#define BFPCTRL_B0BFM (1 << 0) /* Bit 0: RX0BF Pin Operation Mode bit */
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#define BFPCTRL_B1BFM (1 << 1) /* Bit 1: RX1BF Pin Operation Mode bit */
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#define BFPCTRL_B0BFE (1 << 2) /* Bit 2: RX0BF Pin Function Enable bit */
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#define BFPCTRL_B1BFE (1 << 3) /* Bit 3: RX1BF Pin Function Enable bit */
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#define BFPCTRL_B0BFS (1 << 4) /* Bit 4: RX0BF Pin State bit (Digital Output mode only) */
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#define BFPCTRL_B1BFS (1 << 5) /* Bit 5: RX1BF Pin State bit (Digital Output mode only) */
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/* Bits 6-7: Not used */
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/* RXBnSIDH – RECEIVE BUFFER n STANDARD IDENTIFIER HIGH */
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#define RXBSIDH_SID_MASK 0xff /* Standard Identifier bits <10:3> */
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/* RXBnSIDL – RECEIVE BUFFER n STANDARD IDENTIFIER LOW */
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#define RXBSIDL_SID_SHIFT (5) /* Bits 5-7: Standard Identifier bits <2:0> */
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#define RXBSIDL_SID_MASK (0x7 << RXBSIDL_SID_SHIFT)
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#define RXBSIDL_SRR (1 << 4) /* Bit 4: Standard Frame Remote Transmit Request bit (valid only if IDE bit = '0')*/
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#define RXBSIDL_IDE (1 << 3) /* Bit 3: Extended Identifier Message received */
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/* Bit 2: Not used */
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#define RXBSIDL_EID_SHIFT (0) /* Bits 0-1: Extended Identifier bits <17:16> */
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#define RXBSIDL_EID_MASK (0x03 << RXBSIDL_EID_SHIFT)
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/* RXBnEID8 – RECEIVE BUFFER n EXTENDED IDENTIFIER HIGH */
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#define RXBEID8_EID_MASK 0xff /* Bits 0-7: Extended Identifier bits <15:8> */
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/* RXBnEID0 – RECEIVE BUFFER n EXTENDED IDENTIFIER LOW */
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#define RXBEID0_EID_MASK 0xff /* Bits 0-7: Extended Identifier bits <7:0> */
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/* RXBnDLC – RECEIVE BUFFER n DATA LENGHT CODE */
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#define RXBDLC_DLC_SHIFT (0) /* Bits 0-3: Data Length Code <3:0> bits */
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#define RXBDLC_DLC_MASK (0xf << RXBDLC_DLC_SHIFT)
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#define RXBDLC_RB0 (1 << 4) /* Bit 4: Reserved bit 0 */
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#define RXBDLC_RB1 (1 << 5) /* Bit 5: Reserved bit 1 */
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#define RXBDLC_RTR (1 << 6) /* Bit 6: Remote Transmission Request bit */
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/* Bit 7: Not used */
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/* RXFnSIDH – FILTER n STANDARD IDENTIFIER HIGH */
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#define RXFSIDH_SID_MASK 0xff /* Standard Identifier Filter bits <10:3> */
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/* RXFnSIDL – FILTER n STANDARD IDENTIFIER LOW */
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#define RXFSIDL_EID_SHIFT (0) /* Bit 0-1: Extended Identifier Filter bits <17:16> */
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#define RXFSIDL_EID_MASK (3 << RXFSIDL_EID_SHIFT)
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#define RXFSIDL_EXIDE (1 << 3) /* Bit 3: Extended Identifier Enable bit */
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#define RXFSIDL_SID_SHIFT (5) /* Bits 5-7: Standard Identifier Filter bits <2:0> */
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#define RXFSIDL_SID_MASK (0x7 << RXFSIDL_SID_SHIFT)
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/* RXFnEID8 – FILTER n EXTENDED IDENTIFIER HIGH */
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#define RXFEID8_EID_MASK 0xff /* Extended Identifier bits <15:8> */
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/* RXFnEID0 – FILTER n EXTENDED IDENTIFIER LOW */
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#define RXFEID0_EID_MASK 0xff /* Extended Identifier bits <7:0> */
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/* RXMnSIDH – MASK n STANDARD IDENTIFIER HIGH */
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#define RXMSIDH_SID_MASK 0xff /* Standard Identifier Mask bits <10:3> */
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/* RXMnSIDL – MASK n STANDARD IDENTIFIER LOW */
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#define RXMSIDL_EID_SHIFT (0) /* Bits 0-1: Extended Identifier Mask bits <17:16> */
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#define RXMSIDL_EID_MASK (3 << RXMSIDH_EID_SHIFT)
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#define RXMSIDL_SID_SHIFT (5) /* Bits 5-7: Standard Identifier Mask bits <2:0> */
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#define RXMSIDL_MASK (7 << RXMSIDH_SID_SHIFT)
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/* RXMnEID8 – MASK n EXTENDED IDENTIFIER HIGH */
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#define RXMEID8_EID_MASK 0xff /* Extended Identifier bits <15:8> */
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/* RXMnEID0 – MASK n EXTENDED IDENTIFIER LOW */
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#define RXMEID0_EID_MASK 0xff /* Extended Identifier Mask bits <7:0> */
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/* CNF1 – CONFIGURATION 1 */
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#define CNF1_BRP_SHIFT (0) /* Bits 0-5: Baud Rate Prescaler bits <5:0>, TQ = 2 x (BRP + 1)/Fosc */
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#define CNF1_BRP_MASK (0x3f << CNF1_BRP_SHIFT)
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#define CNF1_SJW_SHIFT (6) /* Bit 6-7: Synchronization Jump Width Length bits <1:0> */
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#define CNF1_SJW_MASK (3 << CNF1_SJW_SHIFT)
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# define CNF1_SJW_4xTQ (3 << CNF1_SJW_SHIFT) /* Length = 4 x TQ */
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# define CNF1_SJW_3xTQ (2 << CNF1_SJW_SHIFT) /* Length = 3 x TQ */
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# define CNF1_SJW_2xTQ (1 << CNF1_SJW_SHIFT) /* Length = 2 x TQ */
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# define CNF1_SJW_1xTQ (0 << CNF1_SJW_SHIFT) /* Length = 1 x TQ */
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/* CNF2 – CONFIGURATION 2 */
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#define CNF2_PRSEG_SHIFT (0) /* Bits 0-2: Propagation Segment Length bits <2:0>, (PRSEG + 1) x TQ */
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#define CNF2_PRSEG_MASK (7 << CNF2_PRSEG_SHIFT)
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#define CNF2_PHSEG1_SHIFT (3) /* Bits 3-5: PS1 Length bits <2:0>, (PHSEG1 + 1) x TQ */
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#define CNF2_PHSEG1_MASK (7 << CNF2_PHSEG1_SHIFT)
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#define CNF2_SAM (1 << 6) /* Bit 6: Sample Point Configuration bit */
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#define CNF2_BTLMODE (1 << 7) /* Bit 7: PS2 Bit Time Length bit */
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/* CNF3 - CONFIGURATION 3 */
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#define CNF3_PHSEG2_SHIFT (0) /* Bits 0-2: PS2 Length bits<2:0>, (PHSEG2 + 1) x TQ */
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#define CNF3_PHSEG2_MASK (7 << CNF3_PHSEG2_SHIFT)
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#define CNF3_WAKFIL (1 << 6) /* Bit 3: Wake-up Filter bit */
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#define CNF3_SOF (1 << 7) /* Bit 7: Start-of-Frame signal bit */
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/* TEC – TRANSMIT ERROR COUNTER */
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#define TEC_MASK 0xff /* Transmit Error Count bits <7:0> */
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/* REC – RECEIVER ERROR COUNTER */
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#define REC_MASK 0xff /* Receive Error Count bits <7:0> */
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/* EFLG – ERROR FLAG */
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#define EFLG_EWARN (1 << 0) /* Bit 0: Error Warning Flag bit */
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#define EFLG_RXWAR (1 << 1) /* Bit 1: Receive Error Warning Flag bit */
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#define EFLG_TXWAR (1 << 2) /* Bit 2: Transmit Error Warning Flag bit */
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#define EFLG_RXEP (1 << 3) /* Bit 3: Receive Error-Passive Flag bit */
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#define EFLG_TXEP (1 << 4) /* Bit 4: Transmit Error-Passive Flag bit */
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#define EFLG_TXBO (1 << 5) /* Bit 5: Bus-Off Error Flag bit */
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#define EFLG_RX0OVR (1 << 6) /* Bit 6: Receive Buffer 0 Overflow Flag bit */
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#define EFLG_RX1OVR (1 << 7) /* Bit 7: Receive Buffer 1 Overflow Flag bit */
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/* CANINTE/CANINTF – INTERRUPT ENABLE/FLAG */
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#define MCP2515_INT_RX0 (1 << 0) /* Bit 0: Receive Buffer 0 Full Interrupt Enable bit */
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#define MCP2515_INT_RX1 (1 << 1) /* Bit 1: Receive Buffer 1 Full Interrupt Enable bit */
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#define MCP2515_INT_TX0 (1 << 2) /* Bit 2: Transmit Buffer 0 Empty Interrupt Enable bit */
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#define MCP2515_INT_TX1 (1 << 3) /* Bit 3: Transmit Buffer 1 Empty Interrupt Enable bit */
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#define MCP2515_INT_TX2 (1 << 4) /* Bit 4: Transmit Buffer 2 Empty Interrupt Enable bit */
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#define MCP2515_INT_ERR (1 << 5) /* Bit 5: Error Interrupt Enable bit (multiple sources in EFLG register) */
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#define MCP2515_INT_WAK (1 << 6) /* Bit 6: Wakeup Interrupt Enable bit */
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#define MCP2515_INT_MERR (1 << 7) /* Bit 7: Message Error Interrupt Enable bit */
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|
/* MCP2515 SPI Instruction/Command byte */
|
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|
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|
|
#define MCP2515_RESET 0xC0
|
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|
#define MCP2515_READ 0x03
|
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|
#define MCP2515_READ_RX0 0x90
|
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#define MCP2515_READ_RX1 0x94
|
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|
#define MCP2515_WRITE 0x02
|
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|
#define MCP2515_LOAD_TX0 0x40
|
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|
#define MCP2515_LOAD_TX1 0x42
|
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|
#define MCP2515_LOAD_TX2 0x44
|
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|
#define MCP2515_RTS_TX0 0x81
|
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|
#define MCP2515_RTS_TX1 0x82
|
|||
|
|
#define MCP2515_RTS_TX2 0x84
|
|||
|
|
#define MCP2515_RTS_ALL 0x87
|
|||
|
|
#define MCP2515_READ_STATUS 0xA0
|
|||
|
|
#define MCP2515_RX_STATUS 0xB0
|
|||
|
|
#define MCP2515_BITMOD 0x05
|
|||
|
|
|
|||
|
|
/* CANCTRL register will be 0x87 after reset and in Conf. Mode */
|
|||
|
|
|
|||
|
|
#define DEFAULT_CANCTRL_CONFMODE 0x87
|
|||
|
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|
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|
|
/* Crystal Frequency used on MCP2515 board */
|
|||
|
|
|
|||
|
|
#define MCP2515_CANCLK_FREQUENCY 8000000
|
|||
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