302 lines
13 KiB
C
302 lines
13 KiB
C
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/************************************************************************************
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* arch/arm/src/sama5/sam_dmac.h
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*
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* Copyright (C) 2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAMA5_SAM_DMAC_H
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#define __ARCH_ARM_SRC_SAMA5_SAM_DMAC_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include "chip.h"
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/************************************************************************************
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* Definitions
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************************************************************************************/
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/* Configuration ********************************************************************/
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#ifndef CONFIG_DEBUG
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# undef CONFIG_DEBUG_DMA
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#endif
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/* DMA ******************************************************************************/
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/* Flags used to characterize the desired DMA channel. The naming convention is that
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* one side is the peripheral and the other is memory (however, the interface could still
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* be used if, for example, both sides were memory although the naming would be awkward)
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*/
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/* Select the DMA controller */
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#define DMACH_FLAG_DMAC (1 << 0) /* 0=DMAC0, 1=DMAC1 */
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# define DMACH_FLAG_DMAC0 (0) /* DMAC0 */
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# define DMACH_FLAG_DMAC1 (1 << 0) /* DMAC1 */
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/* Configurable properties of the channel */
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#define DMACH_FLAG_BURST_LARGEST 0 /* Largest length AHB burst */
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#define DMACH_FLAG_BURST_HALF 1 /* Half FIFO size */
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#define DMACH_FLAG_BURST_SINGLE 2 /* Single AHB access */
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#define DMACH_FLAG_FIFOCFG_SHIFT (1) /* Bits 1-2: FIFO configuration */
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#define DMACH_FLAG_FIFOCFG_MASK (3 << DMACH_FLAG_FIFOCFG_SHIFT)
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# define DMACH_FLAG_FIFOCFG_LARGEST (DMACH_FLAG_BURST_LARGEST << DMACH_FLAG_FIFOCFG_SHIFT)
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# define DMACH_FLAG_FIFOCFG_HALF (DMACH_FLAG_BURST_HALF << DMACH_FLAG_FIFOCFG_SHIFT)
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# define DMACH_FLAG_FIFOCFG_SINGLE (DMACH_FLAG_BURST_SINGLE << DMACH_FLAG_FIFOCFG_SHIFT)
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/* Peripheral endpoint characteristics */
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#define DMACH_FLAG_PERIPHPID_SHIFT (3) /* Bits 3-6: Peripheral PID */
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#define DMACH_FLAG_PERIPHPID_MASK (15 << DMACH_FLAG_PERIPHPID_SHIFT)
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#define DMACH_FLAG_PERIPHH2SEL (1 << 7) /* Bits 7: HW handshaking */
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#define DMACH_FLAG_PERIPHISPERIPH (1 << 8) /* Bits 8: 0=memory; 1=peripheral */
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#define DMACH_FLAG_PERIPHWIDTH_SHIFT (9) /* Bits 9-10: Peripheral width */
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#define DMACH_FLAG_PERIPHWIDTH_MASK (3 << DMACH_FLAG_PERIPHWIDTH_SHIFT)
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# define DMACH_FLAG_PERIPHWIDTH_8BITS (0 << DMACH_FLAG_PERIPHWIDTH_SHIFT) /* 8 bits */
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# define DMACH_FLAG_PERIPHWIDTH_16BITS (1 << DMACH_FLAG_PERIPHWIDTH_SHIFT) /* 16 bits */
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# define DMACH_FLAG_PERIPHWIDTH_32BITS (2 << DMACH_FLAG_PERIPHWIDTH_SHIFT) /* 32 bits */
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# define DMACH_FLAG_PERIPHWIDTH_64BITS (3 << DMACH_FLAG_PERIPHWIDTH_SHIFT) /* 64 bits */
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#define DMACH_FLAG_PERIPHINCREMENT (1 << 11) /* Bit 11: Autoincrement peripheral address */
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#define DMACH_FLAG_PERIPHCHUNKSIZE (1 << 12) /* Bit 12: Peripheral chunk size */
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# define DMACH_FLAG_PERIPHCHUNKSIZE_1 (0) /* Peripheral chunksize = 1 */
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# define DMACH_FLAG_PERIPHCHUNKSIZE_4 DMACH_FLAG_PERIPHCHUNKSIZE /* Peripheral chunksize = 4 */
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/* Memory endpoint characteristics */
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#define DMACH_FLAG_MEMPID_SHIFT (13) /* Bits 13-14: Memory PID */
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#define DMACH_FLAG_MEMPID_MASK (15 << DMACH_FLAG_PERIPHPID_SHIFT)
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#define DMACH_FLAG_MEMH2SEL (1 << 15) /* Bits 15: HW handshaking */
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#define DMACH_FLAG_MEMISPERIPH (1 << 16) /* Bits 16: 0=memory; 1=peripheral */
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#define DMACH_FLAG_MEMWIDTH_SHIFT (17) /* Bits 17-18: Memory width */
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#define DMACH_FLAG_MEMWIDTH_MASK (3 << DMACH_FLAG_MEMWIDTH_SHIFT)
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# define DMACH_FLAG_MEMWIDTH_8BITS (0 << DMACH_FLAG_MEMWIDTH_SHIFT) /* 8 bits */
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# define DMACH_FLAG_MEMWIDTH_16BITS (1 << DMACH_FLAG_MEMWIDTH_SHIFT) /* 16 bits */
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# define DMACH_FLAG_MEMWIDTH_32BITS (2 << DMACH_FLAG_MEMWIDTH_SHIFT) /* 32 bits */
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# define DMACH_FLAG_MEMWIDTH_64BITS (3 << DMACH_FLAG_MEMWIDTH_SHIFT) /* 64 bits */
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#define DMACH_FLAG_MEMINCREMENT (1 << 19) /* Bit 19: Autoincrement memory address */
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#define DMACH_FLAG_MEMCHUNKSIZE (1 << 20) /* Bit 20: Memory chunk size */
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# define DMACH_FLAG_MEMCHUNKSIZE_1 (0) /* Memory chunksize = 1 */
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# define DMACH_FLAG_MEMCHUNKSIZE_4 DMACH_FLAG_MEMCHUNKSIZE /* Memory chunksize = 4 */
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/************************************************************************************
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* Public Types
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************************************************************************************/
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typedef FAR void *DMA_HANDLE;
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typedef void (*dma_callback_t)(DMA_HANDLE handle, void *arg, int result);
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/* The following is used for sampling DMA registers when CONFIG DEBUG_DMA is selected */
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#ifdef CONFIG_DEBUG_DMA
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struct sam_dmaregs_s
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{
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/* Global Registers */
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uint32_t gcfg; /* DMAC Global Configuration Register */
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uint32_t en; /* DMAC Enable Register */
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uint32_t sreq; /* DMAC Software Single Request Register */
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uint32_t creq; /* DMAC Software Chunk Transfer Request Register */
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uint32_t last; /* DMAC Software Last Transfer Flag Register */
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uint32_t ebcimr; /* DMAC Error Mask */
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uint32_t ebcisr; /* DMAC Error Status */
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uint32_t chsr; /* DMAC Channel Handler Status Register */
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uint32_t wpmr; /* DMAC Write Protect Mode Register */
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uint32_t wpsr; /* DMAC Write Protect Status Register */
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/* Channel Registers */
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uint32_t saddr; /* DMAC Channel Source Address Register */
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uint32_t daddr; /* DMAC Channel Destination Address Register */
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uint32_t dscr; /* DMAC Channel Descriptor Address Register */
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uint32_t ctrla; /* DMAC Channel Control A Register */
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uint32_t ctrlb; /* DMAC Channel Control B Register */
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uint32_t cfg; /* DMAC Channel Configuration Register */
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uint32_t spip; /* DMAC Channel Source PinP Configuration Register */
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uint32_t dpip; /* DMAC Channel Destination PinP Configuration Register */
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};
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#endif
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/************************************************************************************
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* Inline Functions
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************************************************************************************/
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#ifndef __ASSEMBLY__
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/************************************************************************************
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* Public Data
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************************************************************************************/
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#undef EXTERN
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#if defined(__cplusplus)
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/************************************************************************************
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* Public Function Prototypes
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************************************************************************************/
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/****************************************************************************
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* Name: sam_dmachannel
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*
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* Description:
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* Allocate a DMA channel. This function sets aside a DMA channel with
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* the required FIFO size and flow control capabilities (determined by
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* dma_flags) then gives the caller exclusive access to the DMA channel.
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*
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* The naming convention in all of the DMA interfaces is that one side is
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* the 'peripheral' and the other is 'memory'. Howerver, the interface
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* could still be used if, for example, both sides were memory although
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* the naming would be awkward.
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*
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* Returned Value:
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* If a DMA channel if the required FIFO size is available, this function
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* returns a non-NULL, void* DMA channel handle. NULL is returned on any
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* failure.
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*
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****************************************************************************/
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DMA_HANDLE sam_dmachannel(uint32_t dmach_flags);
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/****************************************************************************
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* Name: sam_dmafree
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*
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* Description:
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* Release a DMA channel. NOTE: The 'handle' used in this argument must
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* NEVER be used again until sam_dmachannel() is called again to re-gain
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* a valid handle.
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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void sam_dmafree(DMA_HANDLE handle);
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/****************************************************************************
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* Name: sam_dmatxsetup
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*
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* Description:
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* Configure DMA for transmit of one buffer (memory to peripheral). This
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* function may be called multiple times to handle large and/or dis-
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* continuous transfers. Calls to sam_dmatxsetup() and sam_dmarxsetup()
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* must not be intermixed on the same transfer, however.
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*
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****************************************************************************/
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int sam_dmatxsetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr,
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size_t nbytes);
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/****************************************************************************
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* Name: sam_dmarxsetup
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*
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* Description:
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* Configure DMA for receipt of one buffer (peripheral to memory). This
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* function may be called multiple times to handle large and/or dis-
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* continuous transfers. Calls to sam_dmatxsetup() and sam_dmarxsetup()
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* must not be intermixed on the same transfer, however.
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*
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****************************************************************************/
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int sam_dmarxsetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr,
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size_t nbytes);
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/****************************************************************************
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* Name: sam_dmastart
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*
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* Description:
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* Start the DMA transfer
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*
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****************************************************************************/
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int sam_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg);
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/****************************************************************************
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* Name: sam_dmastop
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*
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* Description:
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* Cancel the DMA. After sam_dmastop() is called, the DMA channel is
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* reset and sam_dmarx/txsetup() must be called before sam_dmastart() can be
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* called again
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*
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****************************************************************************/
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void sam_dmastop(DMA_HANDLE handle);
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/****************************************************************************
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* Name: sam_dmasample
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*
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* Description:
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* Sample DMA register contents
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*
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****************************************************************************/
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#ifdef CONFIG_DEBUG_DMA
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void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs);
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#else
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# define sam_dmasample(handle,regs)
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#endif
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/****************************************************************************
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* Name: sam_dmadump
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*
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* Description:
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* Dump previously sampled DMA register contents
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*
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****************************************************************************/
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#ifdef CONFIG_DEBUG_DMA
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void sam_dmadump(DMA_HANDLE handle, const struct sam_dmaregs_s *regs,
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const char *msg);
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#else
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# define sam_dmadump(handle,regs,msg)
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#endif
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#undef EXTERN
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#if defined(__cplusplus)
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_ARM_SRC_SAMA5_SAM_DMAC_H */
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