2017-06-11 19:00:29 +02:00
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/************************************************************************************
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* arch/arm/src/stm32/stm32_hrtim.h
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*
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* Copyright (C) 2017 Gregory Nutt. All rights reserved.
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* Author: Mateusz Szafoni <raiden00@railab.me>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32_STM32_HRTIM_H
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#define __ARCH_ARM_SRC_STM32_STM32_HRTIM_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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#ifdef CONFIG_STM32_HRTIM1
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#if defined(CONFIG_STM32_STM32F33XX)
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# include "chip/stm32f33xxx_hrtim.h"
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#else
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# error
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#endif
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/************************************************************************************
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* Pre-processor definitions
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************************************************************************************/
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/* HRTIM Timer X index */
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enum stm32_hrtim_tim_e
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{
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HRTIM_TIMER_MASTER,
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#ifdef CONFIG_STM32_HRTIM_TIMA
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HRTIM_TIMER_TIMA,
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#endif
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#ifdef CONFIG_STM32_HRTIM_TIMB
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HRTIM_TIMER_TIMB,
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#endif
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#ifdef CONFIG_STM32_HRTIM_TIMC
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HRTIM_TIMER_TIMC,
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#endif
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#ifdef CONFIG_STM32_HRTIM_TIMD
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HRTIM_TIMER_TIMD,
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#endif
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#ifdef CONFIG_STM32_HRTIM_TIME
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HRTIM_TIMER_TIME,
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#endif
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};
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/* Source which can force the Tx1/Tx2 output to its inactive state */
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enum stm32_hrtim_out_rst_e
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{
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HRTIM_OUT_RST_UPDATE = (1 << 0),
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HRTIM_OUT_RST_EXTEVNT10 = (1 << 1),
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HRTIM_OUT_RST_EXTEVNT9 = (1 << 2),
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HRTIM_OUT_RST_EXTEVNT8 = (1 << 3),
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HRTIM_OUT_RST_EXTEVNT7 = (1 << 4),
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HRTIM_OUT_RST_EXTEVNT6 = (1 << 5),
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HRTIM_OUT_RST_EXTEVNT5 = (1 << 6),
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HRTIM_OUT_RST_EXTEVNT4 = (1 << 7),
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HRTIM_OUT_RST_EXTEVNT3 = (1 << 8),
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HRTIM_OUT_RST_EXTEVNT2 = (1 << 9),
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HRTIM_OUT_RST_EXTEVNT1 = (1 << 10),
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HRTIM_OUT_RST_TIMEVNT9 = (1 << 11),
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HRTIM_OUT_RST_TIMEVNT8 = (1 << 12),
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HRTIM_OUT_RST_TIMEVNT7 = (1 << 13),
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HRTIM_OUT_RST_TIMEVNT6 = (1 << 14),
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HRTIM_OUT_RST_TIMEVNT5 = (1 << 15),
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HRTIM_OUT_RST_TIMEVNT4 = (1 << 16),
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HRTIM_OUT_RST_TIMEVNT3 = (1 << 17),
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HRTIM_OUT_RST_TIMEVNT2 = (1 << 18),
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HRTIM_OUT_RST_TIMEVNT1 = (1 << 19),
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HRTIM_OUT_RST_MSTCMP4 = (1 << 20),
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HRTIM_OUT_RST_MSTCMP3 = (1 << 21),
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HRTIM_OUT_RST_MSTCMP2 = (1 << 22),
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HRTIM_OUT_RST_MSTCMP1 = (1 << 23),
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HRTIM_OUT_RST_MSTPER = (1 << 24),
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HRTIM_OUT_RST_CMP4 = (1 << 25),
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HRTIM_OUT_RST_CMP3 = (1 << 26),
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HRTIM_OUT_RST_CMP2 = (1 << 27),
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HRTIM_OUT_RST_CMP1 = (1 << 28),
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HRTIM_OUT_RST_PER = (1 << 29),
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HRTIM_OUT_RST_RESYNC = (1 << 30),
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HRTIM_OUT_RST_SOFT = (1 << 31),
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};
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/* Source which can force the Tx1/Tx2 output to its active state */
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enum stm32_hrtim_out_set_e
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{
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HRTIM_OUT_SET_UPDATE = (1 << 0),
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HRTIM_OUT_SET_EXTEVNT10 = (1 << 1),
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HRTIM_OUT_SET_EXTEVNT9 = (1 << 2),
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HRTIM_OUT_SET_EXTEVNT8 = (1 << 3),
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HRTIM_OUT_SET_EXTEVNT7 = (1 << 4),
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HRTIM_OUT_SET_EXTEVNT6 = (1 << 5),
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HRTIM_OUT_SET_EXTEVNT5 = (1 << 6),
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HRTIM_OUT_SET_EXTEVNT4 = (1 << 7),
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HRTIM_OUT_SET_EXTEVNT3 = (1 << 8),
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HRTIM_OUT_SET_EXTEVNT2 = (1 << 9),
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HRTIM_OUT_SET_EXTEVNT1 = (1 << 10),
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HRTIM_OUT_SET_TIMEVNT9 = (1 << 11),
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HRTIM_OUT_SET_TIMEVNT8 = (1 << 12),
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HRTIM_OUT_SET_TIMEVNT7 = (1 << 13),
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HRTIM_OUT_SET_TIMEVNT6 = (1 << 14),
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HRTIM_OUT_SET_TIMEVNT5 = (1 << 15),
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HRTIM_OUT_SET_TIMEVNT4 = (1 << 16),
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HRTIM_OUT_SET_TIMEVNT3 = (1 << 17),
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HRTIM_OUT_SET_TIMEVNT2 = (1 << 18),
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HRTIM_OUT_SET_TIMEVNT1 = (1 << 19),
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HRTIM_OUT_SET_MSTCMP4 = (1 << 20),
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HRTIM_OUT_SET_MSTCMP3 = (1 << 21),
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HRTIM_OUT_SET_MSTCMP2 = (1 << 22),
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HRTIM_OUT_SET_MSTCMP1 = (1 << 23),
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HRTIM_OUT_SET_MSTPER = (1 << 24),
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HRTIM_OUT_SET_CMP4 = (1 << 25),
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HRTIM_OUT_SET_CMP3 = (1 << 26),
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HRTIM_OUT_SET_CMP2 = (1 << 27),
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HRTIM_OUT_SET_CMP1 = (1 << 28),
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HRTIM_OUT_SET_PER = (1 << 29),
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HRTIM_OUT_SET_RESYNC = (1 << 30),
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HRTIM_OUT_SET_SOFT = (1 << 31),
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};
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/* Events that can reset TimerX Counter */
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enum stm32_hrtim_tim_rst_e
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{
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/* Timer owns events */
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HRTIM_RST_UPDT,
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HRTIM_RST_CMP4,
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HRTIM_RST_CMP2,
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/* Master Timer Events */
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HRTIM_RST_MSTCMP4,
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HRTIM_RST_MSTCMP3,
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HRTIM_RST_MSTCMP2,
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HRTIM_RST_MSTCMP1,
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HRTIM_RST_MSTPER,
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/* TimerX events */
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HRTIM_RST_TECMP4,
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HRTIM_RST_TECMP2,
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HRTIM_RST_TECMP1,
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HRTIM_RST_TDCMP4,
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HRTIM_RST_TDCMP2,
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HRTIM_RST_TDCMP1,
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HRTIM_RST_TCCMP4,
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HRTIM_RST_TCCMP2,
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HRTIM_RST_TCCMP1,
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HRTIM_RST_TBCMP4,
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HRTIM_RST_TBCMP2,
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HRTIM_RST_TBCMP1,
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HRTIM_RST_TACMP4,
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HRTIM_RST_TACMP2,
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HRTIM_RST_TACMP1,
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/* External Events */
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HRTIM_RST_EXTEVNT10,
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HRTIM_RST_EXTEVNT9,
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HRTIM_RST_EXTEVNT8,
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HRTIM_RST_EXTEVNT7,
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HRTIM_RST_EXTEVNT6,
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HRTIM_RST_EXTEVNT5,
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HRTIM_RST_EXTEVNT4,
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HRTIM_RST_EXTEVNT3,
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HRTIM_RST_EXTEVNT2,
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HRTIM_RST_EXTEVNT1,
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};
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/* HRTIM Timer X prescaler */
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enum stm32_hrtim_tim_prescaler_e
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{
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HRTIM_PRESCALER_1,
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HRTIM_PRESCALER_2,
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HRTIM_PRESCALER_4,
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HRTIM_PRESCALER_8,
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HRTIM_PRESCALER_16,
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HRTIM_PRESCALER_32,
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HRTIM_PRESCALER_64,
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HRTIM_PRESCALER_128,
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};
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2017-06-11 20:51:23 +02:00
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struct hrtim_dev_s
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{
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#ifdef CONFIG_HRTIM
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/* Fields managed by common upper half HRTIM logic */
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uint8_t hd_ocount; /* The number of times the device has been opened */
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sem_t hd_closesem; /* Locks out new opens while close is in progress */
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#endif
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/* Fields provided by lower half HRTIM logic */
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FAR void *hd_priv; /* Used by the arch-specific logic */
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};
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2017-06-11 19:00:29 +02:00
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/************************************************************************************
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* Public Function Prototypes
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************************************************************************************/
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#ifndef __ASSEMBLY__
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/****************************************************************************
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* Name: stm32_hrtiminitialize
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*
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* Description:
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* Initialize the HRTIM.
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* Valid HRTIM device structure reference on succcess; a NULL on failure.
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*
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* Assumptions:
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* 1. Clock to the HRTIM block has enabled,
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* 2. Board-specific logic has already configured
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*
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****************************************************************************/
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FAR struct hrtim_dev_s* stm32_hrtiminitialize(void);
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2017-06-11 20:51:23 +02:00
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/****************************************************************************
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* Name: hrtim_register
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****************************************************************************/
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int hrtim_register(FAR const char *path, FAR struct hrtim_dev_s *dev);
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2017-06-11 19:00:29 +02:00
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* CONFIG_STM32_HRTIM1 */
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#endif /* __ARCH_ARM_SRC_STM32_STM32_HRTIM_H */
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