2013-01-18 17:37:37 +01:00
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/****************************************************************************
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* arch/lpc17xx/lpc176x_irq.h
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*
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* Copyright (C) 2010-2011, 2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/* This file should never be included directed but, rather, only indirectly
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* through nuttx/irq.h
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*/
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#ifndef __ARCH_ARM_INCLUDE_LPC17XX_LPC176X_IRQ_H
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#define __ARCH_ARM_INCLUDE_LPC17XX_LPC176X_IRQ_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* IRQ numbers. The IRQ number corresponds vector number and hence map
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* directly to bits in the NVIC. This does, however, waste several words of
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* memory in the IRQ to handle mapping tables.
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*/
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/* External interrupts (vectors >= 16) */
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#define LPC17_IRQ_WDT (LPC17_IRQ_EXTINT+0) /* WDT Watchdog Interrupt (WDINT) */
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#define LPC17_IRQ_TMR0 (LPC17_IRQ_EXTINT+1) /* Timer 0 Match 0 - 1 (MR0, MR1)
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* Capture 0 - 1 (CR0, CR1) */
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#define LPC17_IRQ_TMR1 (LPC17_IRQ_EXTINT+2) /* Timer 1 Match 0 - 2 (MR0, MR1, MR2)
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* Capture 0 - 1 (CR0, CR1) */
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#define LPC17_IRQ_TMR2 (LPC17_IRQ_EXTINT+3) /* Timer 2 Match 0-3
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* Capture 0-1 */
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#define LPC17_IRQ_TMR3 (LPC17_IRQ_EXTINT+4) /* Timer 3 Match 0-3
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* Capture 0-1 */
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#define LPC17_IRQ_UART0 (LPC17_IRQ_EXTINT+5) /* UART 0 Rx Line Status (RLS)
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* Transmit Holding Register Empty (THRE)
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* Rx Data Available (RDA)
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* Character Time-out Indicator (CTI)
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* End of Auto-Baud (ABEO)
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* Auto-Baud Time-Out (ABTO) */
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#define LPC17_IRQ_UART1 (LPC17_IRQ_EXTINT+6) /* UART 1 Rx Line Status (RLS)
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* Transmit Holding Register Empty (THRE)
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* Rx Data Available (RDA)
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* Character Time-out Indicator (CTI)
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* Modem Control Change
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* End of Auto-Baud (ABEO)
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* Auto-Baud Time-Out (ABTO) */
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#define LPC17_IRQ_UART2 (LPC17_IRQ_EXTINT+7) /* UART 2 Rx Line Status (RLS)
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* Transmit Holding Register Empty (THRE)
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* Rx Data Available (RDA)
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* Character Time-out Indicator (CTI)
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* End of Auto-Baud (ABEO)
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* Auto-Baud Time-Out (ABTO) */
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#define LPC17_IRQ_UART3 (LPC17_IRQ_EXTINT+8) /* UART 3 Rx Line Status (RLS)
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* Transmit Holding Register Empty (THRE)
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* Rx Data Available (RDA)
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* Character Time-out Indicator (CTI)
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* End of Auto-Baud (ABEO)
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* Auto-Baud Time-Out (ABTO) */
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#define LPC17_IRQ_PWM1 (LPC17_IRQ_EXTINT+9) /* PWM1 Match 0 - 6 of PWM1
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* Capture 0-1 of PWM1 */
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#define LPC17_IRQ_I2C0 (LPC17_IRQ_EXTINT+10) /* I2C0 SI (state change) */
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#define LPC17_IRQ_I2C1 (LPC17_IRQ_EXTINT+11) /* I2C1 SI (state change) */
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#define LPC17_IRQ_I2C2 (LPC17_IRQ_EXTINT+12) /* I2C2 SI (state change) */
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#define LPC17_IRQ_SPIF (LPC17_IRQ_EXTINT+13) /* SPI SPI Interrupt Flag (SPIF)
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* Mode Fault (MODF) */
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#define LPC17_IRQ_SSP0 (LPC17_IRQ_EXTINT+14) /* SSP0 Tx FIFO half empty of SSP0
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* Rx FIFO half full of SSP0
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* Rx Timeout of SSP0
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* Rx Overrun of SSP0 */
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#define LPC17_IRQ_SSP1 (LPC17_IRQ_EXTINT+15) /* SSP 1 Tx FIFO half empty
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* Rx FIFO half full
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* Rx Timeout
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* Rx Overrun */
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#define LPC17_IRQ_PLL0 (LPC17_IRQ_EXTINT+16) /* PLL0 (Main PLL) PLL0 Lock (PLOCK0) */
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#define LPC17_IRQ_RTC (LPC17_IRQ_EXTINT+17) /* RTC Counter Increment (RTCCIF)
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* Alarm (RTCALF) */
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#define LPC17_IRQ_EINT0 (LPC17_IRQ_EXTINT+18) /* External Interrupt 0 (EINT0) */
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#define LPC17_IRQ_EINT1 (LPC17_IRQ_EXTINT+19) /* External Interrupt 1 (EINT1) */
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#define LPC17_IRQ_EINT2 (LPC17_IRQ_EXTINT+20) /* External Interrupt 2 (EINT2) */
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#define LPC17_IRQ_EINT3 (LPC17_IRQ_EXTINT+21) /* External Interrupt 3 (EINT3)
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* Note: EINT3 channel is shared with GPIO interrupts */
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#define LPC17_IRQ_ADC (LPC17_IRQ_EXTINT+22) /* ADC A/D Converter end of conversion */
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#define LPC17_IRQ_BOD (LPC17_IRQ_EXTINT+23) /* BOD Brown Out detect */
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#define LPC17_IRQ_USB (LPC17_IRQ_EXTINT+24) /* USB USB_INT_REQ_LP, USB_INT_REQ_HP,
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* USB_INT_REQ_DMA */
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#define LPC17_IRQ_CAN (LPC17_IRQ_EXTINT+25) /* CAN CAN Common, CAN 0 Tx, CAN 0 Rx,
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* CAN 1 Tx, CAN 1 Rx */
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#define LPC17_IRQ_GPDMA (LPC17_IRQ_EXTINT+26) /* GPDMA IntStatus of DMA channel 0,
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* IntStatus of DMA channel 1 */
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#define LPC17_IRQ_I2S (LPC17_IRQ_EXTINT+27) /* I2S irq, dmareq1, dmareq2 */
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#define LPC17_IRQ_ETH (LPC17_IRQ_EXTINT+28) /* Ethernet WakeupInt, SoftInt, TxDoneInt,
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* TxFinishedInt, TxErrorInt,* TxUnderrunInt,
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* RxDoneInt, RxFinishedInt, RxErrorInt,
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* RxOverrunInt */
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#define LPC17_IRQ_RITINT (LPC17_IRQ_EXTINT+29) /* Repetitive Interrupt Timer (RITINT) */
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#define LPC17_IRQ_MCPWM (LPC17_IRQ_EXTINT+30) /* Motor Control PWM IPER[2:0], IPW[2:0],
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* ICAP[2:0], FES */
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#define LPC17_IRQ_QEI (LPC17_IRQ_EXTINT+31) /* Quadrature Encoder INX_Int, TIM_Int, VELC_Int,
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* DIR_Int, ERR_Int, ENCLK_Int, POS0_Int, POS1_Int
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* POS2_Int, REV_Int, POS0REV_Int, OS1REV_Int,
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* POS2REV_Int */
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#define LPC17_IRQ_PLL1 (LPC17_IRQ_EXTINT+32) /* PLL1 (USB PLL) PLL1 Lock (PLOCK1) */
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#define LPC17_IRQ_USBACT (LPC17_IRQ_EXTINT+33) /* USB Activity Interrupt USB_NEED_CLK */
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#define LPC17_IRQ_CANACT (LPC17_IRQ_EXTINT+34) /* CAN Activity Interrupt CAN1WAKE, CAN2WAKE */
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#define LPC17_IRQ_NEXTINT (35)
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#define LPC17_IRQ_NIRQS (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT)
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/* GPIO interrupts. The LPC17xx supports several interrupts on ports 0 and
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* 2 (only). We go through some special efforts to keep the number of IRQs
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* to a minimum in this sparse interrupt case.
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*
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* 28 interrupts on Port 0: p0.0 - p0.11, p0.15-p0.30
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* 14 interrupts on Port 2: p2.0 - p2.13
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* --
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* 42
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*/
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#ifdef CONFIG_GPIO_IRQ
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# define LPC17_VALID_GPIOINT0 (0x7fff8ffful) /* GPIO port 0 interrrupt set */
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# define LPC17_VALID_GPIOINT2 (0x00003ffful) /* GPIO port 2 interrupt set */
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/* Set 1: 12 interrupts p0.0-p0.11 */
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# define LPC17_VALID_GPIOINT0L (0x00000ffful)
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# define LPC17_VALID_SHIFT0L (0)
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# define LPC17_VALID_FIRST0L (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT)
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# define LPC17_IRQ_P0p0 (LPC17_VALID_FIRST0L+0)
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# define LPC17_IRQ_P0p1 (LPC17_VALID_FIRST0L+1)
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# define LPC17_IRQ_P0p2 (LPC17_VALID_FIRST0L+2)
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# define LPC17_IRQ_P0p3 (LPC17_VALID_FIRST0L+3)
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# define LPC17_IRQ_P0p4 (LPC17_VALID_FIRST0L+4)
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# define LPC17_IRQ_P0p5 (LPC17_VALID_FIRST0L+5)
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# define LPC17_IRQ_P0p6 (LPC17_VALID_FIRST0L+6)
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# define LPC17_IRQ_P0p7 (LPC17_VALID_FIRST0L+7)
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# define LPC17_IRQ_P0p8 (LPC17_VALID_FIRST0L+8)
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# define LPC17_IRQ_P0p9 (LPC17_VALID_FIRST0L+9)
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# define LPC17_IRQ_P0p10 (LPC17_VALID_FIRST0L+10)
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# define LPC17_IRQ_P0p11 (LPC17_VALID_FIRST0L+11)
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# define LPC17_VALID_NIRQS0L (12)
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/* Set 2: 16 interrupts p0.15-p0.30 */
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# define LPC17_VALID_GPIOINT0H (0x7fff8000ull)
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# define LPC17_VALID_SHIFT0H (15)
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# define LPC17_VALID_FIRST0H (LPC17_VALID_FIRST0L+LPC17_VALID_NIRQS0L)
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# define LPC17_IRQ_P0p15 (LPC17_VALID_FIRST0H+0)
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# define LPC17_IRQ_P0p16 (LPC17_VALID_FIRST0H+1)
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# define LPC17_IRQ_P0p17 (LPC17_VALID_FIRST0H+2)
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# define LPC17_IRQ_P0p18 (LPC17_VALID_FIRST0H+3)
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# define LPC17_IRQ_P0p19 (LPC17_VALID_FIRST0H+4)
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# define LPC17_IRQ_P0p20 (LPC17_VALID_FIRST0H+5)
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# define LPC17_IRQ_P0p21 (LPC17_VALID_FIRST0H+6)
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# define LPC17_IRQ_P0p22 (LPC17_VALID_FIRST0H+7)
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# define LPC17_IRQ_P0p23 (LPC17_VALID_FIRST0H+8)
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# define LPC17_IRQ_P0p24 (LPC17_VALID_FIRST0H+9)
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# define LPC17_IRQ_P0p25 (LPC17_VALID_FIRST0H+10)
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# define LPC17_IRQ_P0p26 (LPC17_VALID_FIRST0H+11)
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# define LPC17_IRQ_P0p27 (LPC17_VALID_FIRST0H+12)
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# define LPC17_IRQ_P0p28 (LPC17_VALID_FIRST0H+13)
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# define LPC17_IRQ_P0p29 (LPC17_VALID_FIRST0H+14)
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# define LPC17_IRQ_P0p30 (LPC17_VALID_FIRST0H+15)
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# define LPC17_VALID_NIRQS0H (16)
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/* Set 3: 14 interrupts p2.0-p2.13 */
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# define LPC17_VALID_GPIOINT2 (0x00003ffful)
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# define LPC17_VALID_SHIFT2 (0)
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# define LPC17_VALID_FIRST2 (LPC17_VALID_FIRST0H+LPC17_VALID_NIRQS0H)
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# define LPC17_IRQ_P2p0 (LPC17_VALID_FIRST2+0)
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# define LPC17_IRQ_P2p1 (LPC17_VALID_FIRST2+1)
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# define LPC17_IRQ_P2p2 (LPC17_VALID_FIRST2+2)
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# define LPC17_IRQ_P2p3 (LPC17_VALID_FIRST2+3)
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# define LPC17_IRQ_P2p4 (LPC17_VALID_FIRST2+4)
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# define LPC17_IRQ_P2p5 (LPC17_VALID_FIRST2+5)
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# define LPC17_IRQ_P2p6 (LPC17_VALID_FIRST2+6)
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# define LPC17_IRQ_P2p7 (LPC17_VALID_FIRST2+7)
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# define LPC17_IRQ_P2p8 (LPC17_VALID_FIRST2+8)
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# define LPC17_IRQ_P2p9 (LPC17_VALID_FIRST2+9)
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# define LPC17_IRQ_P2p10 (LPC17_VALID_FIRST2+10)
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# define LPC17_IRQ_P2p11 (LPC17_VALID_FIRST2+11)
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# define LPC17_IRQ_P2p12 (LPC17_VALID_FIRST2+12)
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# define LPC17_IRQ_P2p13 (LPC17_VALID_FIRST2+13)
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# define LPC17_VALID_NIRQS2 (14)
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# define LPC17_NGPIOAIRQS (LPC17_VALID_NIRQS0L+LPC17_VALID_NIRQS0H+LPC17_VALID_NIRQS2)
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#else
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# define LPC17_NGPIOAIRQS (0)
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#endif
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/* Total number of IRQ numbers */
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2013-12-23 18:13:56 +01:00
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#define NR_VECTORS LPC17_IRQ_NIRQS
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2013-01-18 17:37:37 +01:00
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#define NR_IRQS (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT+LPC17_NGPIOAIRQS)
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/****************************************************************************
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* Public Types
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****************************************************************************/
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/****************************************************************************
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* Inline functions
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****************************************************************************/
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/****************************************************************************
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* Public Variables
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****************************************************************************/
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#endif /* __ARCH_ARM_INCLUDE_LPC17XX_LPC176X_IRQ_H */
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