2018-11-16 22:33:01 +01:00
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############################################################################
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# arch/arm/src/max326xx/Make.defs
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#
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2021-03-13 11:24:50 +01:00
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# Licensed to the Apache Software Foundation (ASF) under one or more
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# contributor license agreements. See the NOTICE file distributed with
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# this work for additional information regarding copyright ownership. The
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# ASF licenses this file to you under the Apache License, Version 2.0 (the
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# "License"); you may not use this file except in compliance with the
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# License. You may obtain a copy of the License at
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2018-11-16 22:33:01 +01:00
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#
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2021-03-13 11:24:50 +01:00
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# http://www.apache.org/licenses/LICENSE-2.0
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2018-11-16 22:33:01 +01:00
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#
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2021-03-13 11:24:50 +01:00
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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# License for the specific language governing permissions and limitations
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# under the License.
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2018-11-16 22:33:01 +01:00
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#
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############################################################################
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2018-11-17 16:19:17 +01:00
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# Common ARMv7-M Source Files
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2020-04-30 20:38:27 +02:00
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CMN_ASRCS = arm_saveusercontext.S arm_fullcontextrestore.S arm_switchcontext.S
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2020-05-01 15:28:15 +02:00
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CMN_ASRCS += arm_testset.S arm_fetchadd.S vfork.S
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2018-11-16 22:33:01 +01:00
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2020-04-30 23:19:35 +02:00
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CMN_CSRCS = arm_allocateheap.c arm_assert.c arm_blocktask.c arm_copyfullstate.c
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CMN_CSRCS += arm_createstack.c arm_doirq.c arm_exit.c arm_hardfault.c
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CMN_CSRCS += arm_initialize.c arm_initialstate.c arm_interruptcontext.c
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CMN_CSRCS += arm_mdelay.c arm_memfault.c arm_modifyreg8.c arm_modifyreg16.c
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CMN_CSRCS += arm_modifyreg32.c arm_releasepending.c arm_releasestack.c
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CMN_CSRCS += arm_reprioritizertr.c arm_schedulesigaction.c arm_sigdeliver.c
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CMN_CSRCS += arm_stackframe.c arm_svcall.c arm_trigger_irq.c arm_unblocktask.c
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CMN_CSRCS += arm_udelay.c arm_usestack.c arm_vfork.c
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2018-11-16 22:33:01 +01:00
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ifeq ($(CONFIG_ARMV7M_LAZYFPU),y)
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2020-05-01 15:28:15 +02:00
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CMN_ASRCS += arm_lazyexception.S
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2018-11-16 22:33:01 +01:00
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else
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2020-05-01 15:28:15 +02:00
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CMN_ASRCS += arm_exception.S
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2018-11-16 22:33:01 +01:00
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endif
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2020-04-30 23:19:35 +02:00
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CMN_CSRCS += arm_vectors.c
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2018-11-16 22:33:01 +01:00
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ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
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2020-04-30 23:19:35 +02:00
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CMN_CSRCS += arm_ramvec_initialize.c arm_ramvec_attach.c
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2018-11-16 22:33:01 +01:00
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endif
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ifeq ($(CONFIG_BUILD_PROTECTED),y)
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2020-04-30 23:19:35 +02:00
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CMN_CSRCS += arm_mpu.c arm_task_start.c arm_pthread_start.c
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CMN_CSRCS += arm_signal_dispatch.c
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2020-05-01 15:28:15 +02:00
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CMN_UASRCS += arm_signal_handler.S
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2018-11-16 22:33:01 +01:00
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endif
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ifeq ($(CONFIG_STACK_COLORATION),y)
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2020-04-30 23:19:35 +02:00
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CMN_CSRCS += arm_checkstack.c
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2018-11-16 22:33:01 +01:00
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endif
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ifeq ($(CONFIG_ARCH_FPU),y)
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2020-05-01 15:28:15 +02:00
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CMN_ASRCS += arm_fpu.S
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2020-04-30 20:26:30 +02:00
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CMN_CSRCS += arm_copyarmstate.c
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2018-11-16 22:33:01 +01:00
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endif
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2018-11-17 16:19:17 +01:00
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# Common MAX326XX Source Files
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2018-11-18 23:41:07 +01:00
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CHIP_CSRCS = max326_start.c max326_irq.c max326_clrpend.c
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2018-11-17 16:19:17 +01:00
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2018-11-19 21:36:32 +01:00
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ifeq ($(CONFIG_MAX326XX_ICC),y)
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CHIP_CSRCS += max326_icc.c
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endif
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2018-11-21 19:27:23 +01:00
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ifeq ($(CONFIG_RTC_DRIVER),y)
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CHIP_CSRCS += max326_rtc_lowerhalf.c
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endif
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2018-11-17 16:19:17 +01:00
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# Source Files for the MAX32620 and MAX32630
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# Source Files for the MAX32660
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ifeq ($(CONFIG_ARCH_FAMILY_MAX32660),y)
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2018-11-18 23:41:07 +01:00
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CHIP_CSRCS += max32660_clockconfig.c max32660_lowputc.c max32660_gpio.c
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2018-11-17 16:19:17 +01:00
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endif
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# Configuration-Dependent Source Files
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2018-11-16 22:33:01 +01:00
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ifneq ($(CONFIG_SCHED_TICKLESS),y)
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CHIP_CSRCS += max326_timerisr.c
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else
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CHIP_CSRCS += max326_tickless.c
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endif
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ifeq ($(CONFIG_BUILD_PROTECTED),y)
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CHIP_CSRCS += max326_userspace.c max326_mpuinit.c
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endif
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2018-11-17 20:23:03 +01:00
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ifeq ($(CONFIG_MAX326XX_DMA),y)
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2018-11-17 16:19:17 +01:00
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ifeq ($(CONFIG_ARCH_FAMILY_MAX32660),y)
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CHIP_CSRCS += max32660_dma.c
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endif
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2018-11-16 22:33:01 +01:00
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endif
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ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
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CHIP_CSRCS += max326_idle.c
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endif
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2018-11-17 20:23:03 +01:00
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ifeq ($(CONFIG_MAX326XX_GPIOIRQ),y)
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2018-11-17 16:19:17 +01:00
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ifeq ($(CONFIG_ARCH_FAMILY_MAX32660),y)
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CHIP_CSRCS += max32660_gpioirq.c
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endif
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2018-11-16 22:33:01 +01:00
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endif
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2018-11-21 19:27:23 +01:00
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ifeq ($(CONFIG_MAX326XX_RTC),y)
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ifeq ($(CONFIG_ARCH_FAMILY_MAX32660),y)
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CHIP_CSRCS += max32660_rtc.c
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endif
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endif
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2018-11-21 00:13:35 +01:00
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ifeq ($(CONFIG_MAX32XX_WDT),y)
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2018-11-17 16:19:17 +01:00
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ifeq ($(CONFIG_ARCH_FAMILY_MAX32660),y)
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CHIP_CSRCS += max32660_rtc.c
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endif
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2018-11-16 22:33:01 +01:00
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ifeq ($(CONFIG_RTC_DRIVER),y)
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CHIP_CSRCS += max326_rtc_lowerhalf.c
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endif
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endif
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2018-11-21 00:13:35 +01:00
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ifeq ($(CONFIG_MAX326XX_WDOG),y)
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2018-11-17 16:19:17 +01:00
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ifeq ($(CONFIG_ARCH_FAMILY_MAX32660),y)
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CHIP_CSRCS += max32660_wdt.c
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endif
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2018-11-16 22:33:01 +01:00
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endif
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2018-11-17 20:23:03 +01:00
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ifeq ($(CONFIG_MAX326XX_RNG),y)
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2018-11-16 22:33:01 +01:00
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CHIP_CSRCS += max326_rng.c
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endif
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2018-11-17 16:19:17 +01:00
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ifeq ($(CONFIG_MAX326XX_HAVE_UART),y)
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ifeq ($(CONFIG_ARCH_FAMILY_MAX32660),y)
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CHIP_CSRCS += max32660_serial.c
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endif
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2018-11-16 22:33:01 +01:00
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endif
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ifeq ($(CONFIG_MAX326XX_HAVE_I2CM),y)
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2018-11-17 16:19:17 +01:00
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ifeq ($(CONFIG_ARCH_FAMILY_MAX32660),y)
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CHIP_CSRCS += max32660_i2cm.c
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endif
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2018-11-16 22:33:01 +01:00
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endif
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ifeq ($(CONFIG_MAX326XX_HAVE_SPIM),y)
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2018-11-29 19:12:56 +01:00
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ifeq ($(CONFIG_ARCH_FAMILY_MAX32660),y)
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2018-11-30 01:32:40 +01:00
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ifeq ($(CONFIG_MAX326XX_SPIM0),y)
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2018-11-29 19:12:56 +01:00
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CHIP_CSRCS += max32660_spim.c
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endif
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2018-11-30 01:32:40 +01:00
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ifeq ($(CONFIG_MAX326XX_SPIM1),y)
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CHIP_CSRCS += max32660_spimssm.c
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endif
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endif
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2018-11-16 22:33:01 +01:00
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endif
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2018-11-17 22:36:40 +01:00
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# Paths to source files
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VPATH += chip/common
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ifeq ($(CONFIG_ARCH_FAMILY_MAX32620),y)
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VPATH += chip/max32620_30
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else ifeq ($(CONFIG_ARCH_FAMILY_MAX32630),y)
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VPATH += chip/max32620_30
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endif
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ifeq ($(CONFIG_ARCH_FAMILY_MAX32660),y)
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VPATH += chip/max32660
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endif
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