148 lines
8.2 KiB
C
148 lines
8.2 KiB
C
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/************************************************************************************
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* arch/arm/src/str71x/str71x_bspi.h
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*
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* Copyright (C) 2008 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_STR71X_STR71X_BSPI_H
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#define __ARCH_ARM_SRC_STR71X_STR71X_BSPI_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include <sys/types.h>
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#include "str71x_map.h"
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/************************************************************************************
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* Definitions
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************************************************************************************/
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/* Register Offsets *****************************************************************/
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#define STR71X_BSPI_RXR_OFFSET (0x0000) /* 16-bits wide */
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#define STR71X_BSPI_TXR_OFFSET (0x0004) /* 16-bits wide */
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#define STR71X_BSPI_CSR1_OFFSET (0x0008) /* 16-bits wide */
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#define STR71X_BSPI_CSR2_OFFSET (0x000c) /* 16-bits wide */
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#define STR71X_BSPI_CLK_OFFSET (0x0010) /* 16-bits wide */
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/* Registers ************************************************************************/
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#define STR71X_BSPI_RXR(b) ((b) + STR71X_BSPI_RXR_OFFSET)
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#define STR71X_BSPI_TXR(b) ((b) + STR71X_BSPI_TXR_OFFSET)
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#define STR71X_BSPI_CSR1(b) ((b) + STR71X_BSPI_CSR1_OFFSET)
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#define STR71X_BSPI_CSR2(b) ((b) + STR71X_BSPI_CSR2_OFFSET)
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#define STR71X_BSPI_CLK(b) ((b) + STR71X_BSPI_CLK_OFFSET)
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#define STR71X_BSPI0_RXR (STR71X_BSPI0_BASE + STR71X_BSPI_RXR_OFFSET)
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#define STR71X_BSPI0_TXR (STR71X_BSPI0_BASE + STR71X_BSPI_TXR_OFFSET)
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#define STR71X_BSPI0_CSR1 (STR71X_BSPI0_BASE + STR71X_BSPI_CSR1_OFFSET)
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#define STR71X_BSPI0_CSR2 (STR71X_BSPI0_BASE + STR71X_BSPI_CSR2_OFFSET)
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#define STR71X_BSPI0_CLK (STR71X_BSPI0_BASE + STR71X_BSPI_CLK_OFFSET)
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#define STR71X_BSPI1_RXR (STR71X_BSPI1_BASE + STR71X_BSPI_RXR_OFFSET)
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#define STR71X_BSPI1_TXR (STR71X_BSPI1_BASE + STR71X_BSPI_TXR_OFFSET)
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#define STR71X_BSPI1_CSR1 (STR71X_BSPI1_BASE + STR71X_BSPI_CSR1_OFFSET)
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#define STR71X_BSPI1_CSR2 (STR71X_BSPI1_BASE + STR71X_BSPI_CSR2_OFFSET)
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#define STR71X_BSPI1_CLK (STR71X_BSPI1_BASE + STR71X_BSPI_CLK_OFFSET)
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/* Register bit settings ***********************************************************/
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/* BSPI control/status register 1 */
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#define STR71X_BSPICSR1_BSPE 0x0001 /* Bit 0: BSPI enable */
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#define STR71X_BSPICSR1_MSTR 0x0002 /* Bit 1: Master/Slave select */
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#define STR71X_BSPICSR1_RIEMASK 0x000c /* Bit 2-3: BSPI receive interrupt enable */
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#define STR71X_BSPICSR1_RIEDISABLED 0x0000 /* Disabled */
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#define STR71X_BSPICSR1_RIERFNE 0x0004 /* Receive FIFO not empty */
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#define STR71X_BSPICSR1_RIERFF 0x000c /* Receive FIFO full */
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#define STR71X_BSPICSR1_BEIE 0x0080 /* Bit 7: Bus error interrupt enable */
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#define STR71X_BSPICSR1_CPOL 0x0100 /* Bit 8: Clock polarity select */
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#define STR71X_BSPICSR1_CPHA 0x0200 /* Bit 9: Clock phase select */
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#define STR71X_BSPICSR1_WLMASK 0x0c00 /* Bits 10-11: Word length */
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#define STR71X_BSPICSR1_WL8BIT 0x0000 /* 8-bits */
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#define STR71X_BSPICSR1_WL16BIT 0x0400 /* 16-bits */
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#define STR71X_BSPICSR1_RFEMASK 0xf000 /* Bits 12-15: Receive FIFO enable */
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#define STR71X_BSPICSR1_RFE1 0x0000 /* Word 1 enabled */
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#define STR71X_BSPICSR1_RFE12 0x1000 /* Word 1-2 enabled */
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#define STR71X_BSPICSR1_RFE13 0x2000 /* Word 1-3 enabled */
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#define STR71X_BSPICSR1_RFE14 0x3000 /* Word 1-4 enabled */
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#define STR71X_BSPICSR1_RFE15 0x4000 /* Word 1-5 enabled */
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#define STR71X_BSPICSR1_RFE16 0x5000 /* Word 1-6 enabled */
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#define STR71X_BSPICSR1_RFE17 0x6000 /* Word 1-7 enabled */
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#define STR71X_BSPICSR1_RFE18 0x7000 /* Word 1-8 enabled */
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#define STR71X_BSPICSR1_RFE19 0x8000 /* Word 1-9 enabled */
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#define STR71X_BSPICSR1_RFE110 0x9000 /* Word 1-10 enabled */
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/* BSPI control/status register 1 */
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#define STR71X_BSPICSR2_DFIFO 0x0000 /* Bit 0: FIFO disable */
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#define STR71X_BSPICSR2_BERR 0x0000 /* Bit 2: Bus error */
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#define STR71X_BSPICSR2_RFNE 0x0000 /* Bit 3: Receiver FIFO not empty */
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#define STR71X_BSPICSR2_RFF 0x0000 /* Bit 4: Receiver FIFO full */
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#define STR71X_BSPICSR2_ROFL 0x0000 /* Bit 5: Receiver overflow */
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#define STR71X_BSPICSR2_TFE 0x0000 /* Bit 6: Transmit FIFO empty */
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#define STR71X_BSPICSR2_TUFL 0x0000 /* Bit 7: Transmit FIFO underflow */
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#define STR71X_BSPICSR2_TFF 0x0000 /* Bit 8: Transmit FIFO full */
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#define STR71X_BSPICSR2_TFNE 0x0000 /* Bit 9: Transmit FIFO not empty */
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#define STR71X_BSPICSR2_TFEMASK 0x3c00 /* Bit 10-13: Transmit FIFO enable*/
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#define STR71X_BSPICSR2_TFE1 0x0000 /* Word 1 enabled */
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#define STR71X_BSPICSR2_TFE12 0x0000 /* Word 1-2 enabled */
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#define STR71X_BSPICSR2_TFE13 0x0000 /* Word 1-3 enabled */
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#define STR71X_BSPICSR2_TFE14 0x0000 /* Word 1-4 enabled */
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#define STR71X_BSPICSR2_TFE15 0x0000 /* Word 1-5 enabled */
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#define STR71X_BSPICSR2_TFE16 0x0000 /* Word 1-6 enabled */
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#define STR71X_BSPICSR2_TFE17 0x0000 /* Word 1-7 enabled */
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#define STR71X_BSPICSR2_TFE18 0x0000 /* Word 1-8 enabled */
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#define STR71X_BSPICSR2_TFE19 0x0000 /* Word 1-9 enabled */
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#define STR71X_BSPICSR2_TFE110 0x0000 /* Word 1-10 enabled */
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#define STR71X_BSPICSR2_TIEMASK 0xc000 /* Bit 14-15: BSPI transmit interrupt enable */
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#define STR71X_BSPICSR2_TIEDISABLED 0x0000 /* Disabled */
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#define STR71X_BSPICSR2_TIETFE 0x4000 /* Interrupt on transmit FIFO empty */
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#define STR71X_BSPICSR2_TIETUFL 0x8000 /* Interrupt on transmit underlow */
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#define STR71X_BSPICSR2_TIETFF 0xc000 /* Interrupt on transmit FIFO full */
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/************************************************************************************
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* Public Data
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************************************************************************************/
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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#endif /* __ARCH_ARM_SRC_STR71X_STR71X_BSPI_H */
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