2013-07-18 23:20:47 +02:00
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/************************************************************************************
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2013-07-19 19:43:04 +02:00
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* arch/arm/src/armv7-a/sctlr.h
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2013-07-18 23:20:47 +02:00
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* CP15 System Control Registers
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*
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* Copyright (C) 2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* References:
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*
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* "Cortex-A5<41> MPCore, Technical Reference Manual", Revision: r0p1, Copyright <EFBFBD> 2010
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* ARM. All rights reserved. ARM DDI 0434B (ID101810)
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* "ARM<EFBFBD> Architecture Reference Manual, ARMv7-A and ARMv7-R edition", Copyright <EFBFBD>
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* 1996-1998, 2000, 2004-2012 ARM. All rights reserved. ARM DDI 0406C.b (ID072512)
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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2013-07-19 19:43:04 +02:00
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#ifndef __ARCH_ARM_SRC_ARMV7_A_SCTLR_H
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#define __ARCH_ARM_SRC_ARMV7_A_SCTLR_H
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2013-07-18 23:20:47 +02:00
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/************************************************************************************
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* Included Files
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************************************************************************************/
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Reference: Cortex-A5<41> MPCore Paragraph 4.2, "Register summary." */
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/* Main ID Register (MIDR) */
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/* TODO: To be provided */
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/* Cache Type Register (CTR) */
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/* TODO: To be provided */
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/* TCM Type Register
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*
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* The Cortex-A5 MPCore processor does not implement instruction or data Tightly
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* Coupled Memory (TCM), so this register always Reads-As-Zero (RAZ).
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*
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* TLB Type Register
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*
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* The Cortex-A5 MPCore processor does not implement instruction or data Tightly
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* CoupledMemory (TCM), so this register always Reads-As-Zero (RAZ).
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*/
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/* Multiprocessor Affinity Register (MPIDR) */
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/* TODO: To be provided */
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/* Processor Feature Register 0 (ID_PFR0) */
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/* TODO: To be provided */
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/* Processor Feature Register 1 (ID_PFR1) */
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/* TODO: To be provided */
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/* Debug Feature Register 0 (ID_DFR0) */
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/* TODO: To be provided */
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/* Auxiliary Feature Register 0 (ID_AFR0) */
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/* TODO: To be provided */
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/* Memory Model Features Register 0 (ID_MMFR0) */
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/* Memory Model Features Register 1 (ID_MMFR1) */
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/* Memory Model Features Register 2 (ID_MMFR2) */
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/* Memory Model Features Register 3 (ID_MMFR3) */
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/* TODO: To be provided */
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/* Instruction Set Attributes Register 0 (ID_ISAR0) */
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/* Instruction Set Attributes Register 1 (ID_ISAR1) */
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/* Instruction Set Attributes Register 2 (ID_ISAR2) */
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/* Instruction Set Attributes Register 3 (ID_ISAR3) */
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/* Instruction Set Attributes Register 4 (ID_ISAR4) */
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/* Instruction Set Attributes Register 5 (ID_ISAR5) */
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/* Instruction Set Attributes Register 6-7 (ID_ISAR6-7). Reserved. */
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/* TODO: Others to be provided */
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/* Cache Size Identification Register (CCSIDR) */
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/* TODO: To be provided */
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/* Cache Level ID Register (CLIDR) */
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/* TODO: To be provided */
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/* Auxiliary ID Register (AIDR) */
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/* TODO: To be provided */
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/* Cache Size Selection Register (CSSELR) */
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/* TODO: To be provided */
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/* System Control Register (SCTLR)
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*
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* NOTES:
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* (1) Always enabled on A5
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* (2) Not available on A5
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*/
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#define SCTLR_M (1 << 0) /* Bit 0: Enables the MMU */
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#define SCTLR_A (1 << 1) /* Bit 1: Enables strict alignment of data */
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#define SCTLR_C (1 << 2) /* Bit 2: Determines if data can be cached */
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/* Bits 3-9: Reserved */
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#define SCTLR_SW (1 << 10) /* Bit 10: SWP/SWPB Enable bit */
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#define SCTLR_Z (1 << 11) /* Bit 11: Program flow prediction control (1) */
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#define SCTLR_I (1 << 12) /* Bit 12: Determines if instructions can be cached */
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#define SCTLR_V (1 << 13) /* Bit 13: Vectors bit */
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#define SCTLR_RR (1 << 14) /* Bit 14: Cache replacement strategy (2) */
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/* Bits 15-16: Reserved */
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#define SCTLR_HA (1 << 17) /* Bit 17: Hardware management access disabled (2) */
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/* Bits 18-24: Reserved */
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#define SCTLR_EE (1 << 25) /* Bit 25: Determines the value the CPSR.E */
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/* Bits 26-27: Reserved */
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#define SCTLR_TRE (1 << 28) /* Bit 28: TEX remap */
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#define SCTLR_AFE (1 << 29) /* Bit 29: Access Flag Enable bit */
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#define SCTLR_TE (1 << 30) /* Bit 30: Thumb exception enable */
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/* Bit 31: Reserved */
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/* Auxiliary Control Register (ACTLR) */
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/* TODO: To be provided */
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/* Coprocessor Access Control Register (CPACR) */
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/* TODO: To be provided */
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/* Secure Configuration Register (SCR) */
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/* TODO: To be provided */
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/* Secure Debug Enable Register (SDER) */
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/* TODO: To be provided */
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/* Non-secure Access Control Register (NSACR) */
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/* Bits 0-9: Reserved */
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#define NSACR_CP10 (1 << 10) /* Bit 10: Permission to access coprocessor 10 */
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#define NSACR_CP11 (1 << 11) /* Bit 11: Permission to access coprocessor 11 */
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/* Bits 12-13: Reserved */
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#define NSACR_NSD32DIS (1 << 14) /* Bit 14: Disable the Non-secure use of VFP D16-D31 */
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#define NSACR_NSASEDIS (1 << 15) /* Bit 15: Disable Non-secure Advanced SIMD Extension */
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/* Bits 16-17: Reserved */
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#define NSACR_NSSMP (1 << 18) /* Bit 18: ACR SMP bit writable */
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/* Bits 19-31: Reserved */
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/* Virtualization Control Register (VCR) */
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/* TODO: To be provided */
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/* Translation Table Base Register 0 (TTBR0). See mmu.h */
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/* Translation Table Base Register 1 (TTBR1). See mmu.h */
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/* Translation Table Base Control Register (TTBCR). See mmu.h */
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/* Domain Access Control Register (DACR). See mmu.h */
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/* Data Fault Status Register (DFSR). See mmu.h */
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/* Instruction Fault Status Register (IFSR). See mmu.h */
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/* Auxiliary Data Fault Status Register (ADFSR). Not used in this implementation. */
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/* Data Fault Address Register(DFAR)
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*
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* Holds the MVA of the faulting address when a synchronous fault occurs
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*
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* Instruction Fault Address Register(IFAR)
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*
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* Holds the MVA of the faulting address of the instruction that caused a prefetch
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* abort.
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*
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* NOP Register
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*
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* The use of this register is optional and deprecated. Use the NOP instruction
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* instead.
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*
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* Physical Address Register (PAR)
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*
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* Holds:
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* - the PA after a successful translation
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* - the source of the abort for an unsuccessful translation
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*
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* Instruction Synchronization Barrier
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*
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* The use of ISB is optional and deprecated. Use the instruction ISB instead.
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*
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* Data Memory Barrier
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* The use of DMB is deprecated and, on Cortex-A5 MPCore, behaves as NOP. Use the
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* instruction DMB instead.
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*/
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/* Vector Base Address Register (VBAR) */
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/* TODO: To be provided */
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/* Monitor Vector Base Address Register (MVBAR) */
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/* TODO: To be provided */
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/* Interrupt Status Register (ISR) */
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/* TODO: To be provided */
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/* Virtualization Interrupt Register (VIR) */
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/* TODO: To be provided */
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/* Context ID Register (CONTEXTIDR) */
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#define CONTEXTIDR_ASID_SHIFT (0) /* Bits 0-7: Address Space Identifier */
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#define CONTEXTIDR_ASID_MASK (0xff << CONTEXTIDR_ASID_SHIFT)
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#define CONTEXTIDR_PROCID_SHIFT (8) /* Bits 8-31: Process Identifier */
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#define CONTEXTIDR_PROCID_MASK (0x00ffffff << CONTEXTIDR_PROCID_SHIFT)
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/* Configuration Base Address Register (CBAR) */
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/* TODO: To be provided */
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/************************************************************************************
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* Assemby Macros
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************************************************************************************/
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#ifdef __ASSEMBLY__
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/* Get the device ID */
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.macro cp15_rdid, id
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mrc p15, 0, \id, c0, c0, 0
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.endm
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2013-07-19 19:43:04 +02:00
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/* Read/write the system control register (SCTLR) */
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2013-07-19 19:43:04 +02:00
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.macro cp15_rdsctlr, sctlr
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mrc p15, 0, \sctlr, c1, c0, 0
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.endm
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2013-07-19 19:43:04 +02:00
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.macro cp15_wrsctlr, sctlr
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mcr p15, 0, \sctlr, c1, c0, 0
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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.endm
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#endif /* __ASSEMBLY__ */
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/************************************************************************************
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* Inline Functions
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************************************************************************************/
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#ifndef __ASSEMBLY__
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/* Get the device ID */
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static inline unsigned int cp15_rdid(void)
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{
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unsigned int id;
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__asm__ __volatile__
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(
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"\tmrc p15, 0, %0, c0, c0, 0"
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: "=r" (id)
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:
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: "memory"
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);
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return id;
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}
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/* Read/write the system control register (SCTLR) */
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2013-07-19 19:43:04 +02:00
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static inline unsigned int cp15_rdsctlr(void)
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{
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unsigned int sctlr;
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__asm__ __volatile__
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(
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2013-07-30 01:54:56 +02:00
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"\tmrc p15, 0, %0, c1, c0, 0\n"
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: "=r" (sctlr)
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:
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: "memory"
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);
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2013-07-19 19:43:04 +02:00
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return sctlr;
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2013-07-18 23:20:47 +02:00
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}
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2013-07-19 19:43:04 +02:00
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static inline void cp15_wrsctlr(unsigned int sctlr)
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{
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__asm__ __volatile__
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(
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2013-07-30 01:54:56 +02:00
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"\tmcr p15, 0, %0, c1, c0, 0\n"
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"\tnop\n"
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"\tnop\n"
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"\tnop\n"
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"\tnop\n"
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"\tnop\n"
|
|
|
|
|
"\tnop\n"
|
|
|
|
|
"\tnop\n"
|
|
|
|
|
"\tnop\n"
|
|
|
|
|
:
|
2013-07-19 19:43:04 +02:00
|
|
|
|
: "r" (sctlr)
|
2013-07-18 23:20:47 +02:00
|
|
|
|
: "memory"
|
|
|
|
|
);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#endif /* __ASSEMBLY__ */
|
|
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
|
* Public Variables
|
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
|
* Public Function Prototypes
|
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
|
|
#ifndef __ASSEMBLY__
|
|
|
|
|
#ifdef __cplusplus
|
|
|
|
|
#define EXTERN extern "C"
|
|
|
|
|
extern "C" {
|
|
|
|
|
#else
|
|
|
|
|
#define EXTERN extern
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#undef EXTERN
|
|
|
|
|
#ifdef __cplusplus
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
#endif /* __ASSEMBLY__ */
|
|
|
|
|
|
2013-07-19 19:43:04 +02:00
|
|
|
|
#endif /* __ARCH_ARM_SRC_ARMV7_A_SCTLR_H */
|