2014-01-28 21:35:03 +01:00
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/****************************************************************************
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2019-08-15 18:19:17 +02:00
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* boards/arm/sama5/sama5d3x-ek/scripts/nor-ddram.ld
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2014-01-28 21:35:03 +01:00
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*
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2021-03-17 18:14:12 +01:00
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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2014-01-28 21:35:03 +01:00
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*
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2021-03-17 18:14:12 +01:00
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* http://www.apache.org/licenses/LICENSE-2.0
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2014-01-28 21:35:03 +01:00
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*
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2021-03-17 18:14:12 +01:00
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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2014-01-28 21:35:03 +01:00
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*
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****************************************************************************/
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/* The SAMA5D3x-EK has 128MB of NOR flash at CS0 (0x1000:0000). In this
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* configuration, the .text and a copy of the .data section will be loaded
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* into NOR flash. NuttX .data, .bss, the IDLE stack, and the primary
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* heap will be allocated in SRAM. The SAMA5D3 has 128 KB of ISRAM beginning
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* at virtual address 0x0030:0000.
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*
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* The SAMA5D3 has 128 KB of ISRAM beginning at virtual address 0x0030:0000
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* And 256Mb of SDRAm at address 0x2000:0000. This script assumes ISRAM used
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* only for the page table. All variables are retained in SDRAM.
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*
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* Vectors in low memory are assumed to reside at the beginning of NOR flash.
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*/
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MEMORY
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{
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2019-09-15 23:27:58 +02:00
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norflash (W!RX) : ORIGIN = 0x10000000, LENGTH = 128M
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isram (WR) : ORIGIN = 0x00304000, LENGTH = 128K - 16K
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sdram (W!RX) : ORIGIN = 0x20000000, LENGTH = 256K
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2014-01-28 21:35:03 +01:00
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}
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ENTRY(entry)
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ENTRY(_stext)
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SECTIONS
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{
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2019-09-15 23:27:58 +02:00
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.text :
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{
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_stext = ABSOLUTE(.);
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*(.vectors)
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*(.text .text.*)
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*(.fixup)
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*(.gnu.warning)
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*(.rodata .rodata.*)
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*(.gnu.linkonce.t.*)
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*(.glue_7)
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*(.glue_7t)
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*(.got)
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*(.gcc_except_table)
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*(.gnu.linkonce.r.*)
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*(.ARM.extab*)
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*(.gnu.linkonce.armextab.*)
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_etext = ABSOLUTE(.);
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} > norflash
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2014-01-28 21:35:03 +01:00
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2019-09-15 23:27:58 +02:00
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.init_section :
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{
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_sinit = ABSOLUTE(.);
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2023-02-27 07:21:36 +01:00
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KEEP(*(.init_array .init_array.*))
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2019-09-15 23:27:58 +02:00
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_einit = ABSOLUTE(.);
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} > norflash
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2014-01-28 21:35:03 +01:00
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2019-09-15 23:27:58 +02:00
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.ARM.extab :
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{
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*(.ARM.extab*)
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} > norflash
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2014-01-28 21:35:03 +01:00
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2019-09-15 23:27:58 +02:00
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/* .ARM.exidx is sorted, so has to go in its own output section. */
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2014-01-28 21:35:03 +01:00
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2019-09-15 23:27:58 +02:00
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PROVIDE_HIDDEN (__exidx_start = .);
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.ARM.exidx :
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{
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*(.ARM.exidx* .gnu.linkonce.armexidx.*)
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} > norflash
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PROVIDE_HIDDEN (__exidx_end = .);
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2014-01-28 21:35:03 +01:00
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2019-09-15 23:27:58 +02:00
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.data :
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{
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_sdata = ABSOLUTE(.);
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*(.data .data.*)
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*(.gnu.linkonce.d.*)
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CONSTRUCTORS
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2019-09-16 01:22:16 +02:00
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. = ALIGN(4);
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2019-09-15 23:27:58 +02:00
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_edata = ABSOLUTE(.);
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} > sdram AT > norflash
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2014-01-28 21:35:03 +01:00
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2019-09-15 23:27:58 +02:00
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_eronly = LOADADDR(.data);
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2014-01-28 21:35:03 +01:00
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2019-09-15 23:27:58 +02:00
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.bss :
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{
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_sbss = ABSOLUTE(.);
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*(.bss .bss.*)
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*(.gnu.linkonce.b.*)
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*(COMMON)
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2019-09-16 02:06:36 +02:00
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. = ALIGN(4);
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2019-09-15 23:27:58 +02:00
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_ebss = ABSOLUTE(.);
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} > sdram
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2014-01-28 21:35:03 +01:00
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2019-09-15 23:27:58 +02:00
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/* Uninitialized data */
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2016-05-13 16:05:21 +02:00
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2019-09-15 23:27:58 +02:00
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.noinit :
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{
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_snoinit = ABSOLUTE(.);
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*(.noinit*)
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_enoinit = ABSOLUTE(.);
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} > sdram
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2016-05-13 16:05:21 +02:00
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2019-09-15 23:27:58 +02:00
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/* Stabs debugging sections. */
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2016-05-13 16:05:21 +02:00
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2019-09-15 23:27:58 +02:00
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.stab 0 : { *(.stab) }
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.stabstr 0 : { *(.stabstr) }
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.stab.excl 0 : { *(.stab.excl) }
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.stab.exclstr 0 : { *(.stab.exclstr) }
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.stab.index 0 : { *(.stab.index) }
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.stab.indexstr 0 : { *(.stab.indexstr) }
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.comment 0 : { *(.comment) }
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.debug_abbrev 0 : { *(.debug_abbrev) }
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.debug_info 0 : { *(.debug_info) }
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.debug_line 0 : { *(.debug_line) }
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.debug_pubnames 0 : { *(.debug_pubnames) }
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.debug_aranges 0 : { *(.debug_aranges) }
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2014-01-28 21:35:03 +01:00
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}
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