287 lines
11 KiB
C
287 lines
11 KiB
C
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/****************************************************************************
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* drivers/wireless/ieee802154/mrf24j40/mrf24j40_reg.h
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*
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* Copyright (C) 2015-2016 Sebastien Lorquet. All rights reserved.
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* Copyright (C) 2017 Verge Inc. All rights reserved.
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* Author: Sebastien Lorquet <sebastien@lorquet.fr>
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* Author: Anthony Merlino <anthony@vergeaero.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/* MRF24J40 Registers *******************************************************/
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#define MRF24J40_RXMCR 0x00
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#define MRF24J40_PANIDL 0x01
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#define MRF24J40_PANIDH 0x02
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#define MRF24J40_SADRL 0x03
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#define MRF24J40_SADRH 0x04
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#define MRF24J40_EADR0 0x05
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#define MRF24J40_EADR1 0x06
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#define MRF24J40_EADR2 0x07
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#define MRF24J40_EADR3 0x08
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#define MRF24J40_EADR4 0x09
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#define MRF24J40_EADR5 0x0A
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#define MRF24J40_EADR6 0x0B
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#define MRF24J40_EADR7 0x0C
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#define MRF24J40_RXFLUSH 0x0D
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#define MRF24J40_ORDER 0x10
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#define MRF24J40_TXMCR 0x11
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#define MRF24J40_ACKTMOUT 0x12
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#define MRF24J40_ESLOTG1 0x13
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#define MRF24J40_SYMTICKL 0x14
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#define MRF24J40_SYMTICKH 0x15
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#define MRF24J40_PACON0 0x16
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#define MRF24J40_PACON1 0x17
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#define MRF24J40_PACON2 0x18
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#define MRF24J40_TXBCON0 0x1A
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#define MRF24J40_TXNCON 0x1B
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#define MRF24J40_TXG1CON 0x1C
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#define MRF24J40_TXG2CON 0x1D
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#define MRF24J40_ESLOTG23 0x1E
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#define MRF24J40_ESLOTG45 0x1F
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#define MRF24J40_ESLOTG67 0x20
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#define MRF24J40_TXPEND 0x21
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#define MRF24J40_WAKECON 0x22
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#define MRF24J40_FRMOFFSET 0x23
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#define MRF24J40_TXSTAT 0x24
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#define MRF24J40_TXBCON1 0x25
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#define MRF24J40_GATECLK 0x26
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#define MRF24J40_TXTIME 0x27
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#define MRF24J40_HSYMTMRL 0x28
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#define MRF24J40_HSYMTMRH 0x29
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#define MRF24J40_SOFTRST 0x2A
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#define MRF24J40_SECCON0 0x2C
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#define MRF24J40_SECCON1 0x2C
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#define MRF24J40_TXSTBL 0x2E
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#define MRF24J40_RXSR 0x30
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#define MRF24J40_INTSTAT 0x31
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#define MRF24J40_INTCON 0x32
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#define MRF24J40_GPIO 0x33
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#define MRF24J40_TRISGPIO 0x34
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#define MRF24J40_SLPACK 0x35
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#define MRF24J40_RFCTL 0x36
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#define MRF24J40_SECCR2 0x37
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#define MRF24J40_BBREG0 0x38
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#define MRF24J40_BBREG1 0x39
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#define MRF24J40_BBREG2 0x3A
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#define MRF24J40_BBREG3 0x3B
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#define MRF24J40_BBREG4 0x3C
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#define MRF24J40_BBREG6 0x3E
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#define MRF24J40_CCAEDTH 0x3F
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#define MRF24J40_FIFO_BASE 0x80000000
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#define MRF24J40_LONGREG_BASE 0x80000200
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#define MRF24J40_RXBUF_BASE 0x80000300
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#define MRF24J40_TXNORM_FIFO (MRF24J40_FIFO_BASE + 0x000)
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#define MRF24J40_BEACON_FIFO (MRF24J40_FIFO_BASE + 0x080)
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#define MRF24J40_GTS1_FIFO (MRF24J40_FIFO_BASE + 0x100)
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#define MRF24J40_GTS2_FIFO (MRF24J40_FIFO_BASE + 0x180)
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#define MRF24J40_RFCON0 (MRF24J40_LONGREG_BASE + 0x00)
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#define MRF24J40_RFCON1 (MRF24J40_LONGREG_BASE + 0x01)
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#define MRF24J40_RFCON2 (MRF24J40_LONGREG_BASE + 0x02)
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#define MRF24J40_RFCON3 (MRF24J40_LONGREG_BASE + 0x03)
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#define MRF24J40_RFCON5 (MRF24J40_LONGREG_BASE + 0x05)
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#define MRF24J40_RFCON6 (MRF24J40_LONGREG_BASE + 0x06)
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#define MRF24J40_RFCON7 (MRF24J40_LONGREG_BASE + 0x07)
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#define MRF24J40_RFCON8 (MRF24J40_LONGREG_BASE + 0x08)
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#define MRF24J40_SLPCAL0 (MRF24J40_LONGREG_BASE + 0x09)
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#define MRF24J40_SLPCAL1 (MRF24J40_LONGREG_BASE + 0x0A)
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#define MRF24J40_SLPCAL2 (MRF24J40_LONGREG_BASE + 0x0B)
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#define MRF24J40_RFSTATE (MRF24J40_LONGREG_BASE + 0x0F)
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#define MRF24J40_RSSI (MRF24J40_LONGREG_BASE + 0x10)
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#define MRF24J40_SLPCON0 (MRF24J40_LONGREG_BASE + 0x11)
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#define MRF24J40_SLPCON1 (MRF24J40_LONGREG_BASE + 0x20)
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#define MRF24J40_WAKETIMEL (MRF24J40_LONGREG_BASE + 0x22)
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#define MRF24J40_WAKETIMEH (MRF24J40_LONGREG_BASE + 0x23)
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#define MRF24J40_REMCNTL (MRF24J40_LONGREG_BASE + 0x24)
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#define MRF24J40_REMCNTH (MRF24J40_LONGREG_BASE + 0x25)
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#define MRF24J40_MAINCNT0 (MRF24J40_LONGREG_BASE + 0x26)
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#define MRF24J40_MAINCNT1 (MRF24J40_LONGREG_BASE + 0x27)
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#define MRF24J40_MAINCNT2 (MRF24J40_LONGREG_BASE + 0x28)
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#define MRF24J40_MAINCNT3 (MRF24J40_LONGREG_BASE + 0x29)
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#define MRF24J40_TESTMODE (MRF24J40_LONGREG_BASE + 0x2F)
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#define MRF24J40_ASSOEADR0 (MRF24J40_LONGREG_BASE + 0x30)
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#define MRF24J40_ASSOEADR1 (MRF24J40_LONGREG_BASE + 0x31)
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#define MRF24J40_ASSOEADR2 (MRF24J40_LONGREG_BASE + 0x32)
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#define MRF24J40_ASSOEADR3 (MRF24J40_LONGREG_BASE + 0x33)
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#define MRF24J40_ASSOEADR4 (MRF24J40_LONGREG_BASE + 0x34)
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#define MRF24J40_ASSOEADR5 (MRF24J40_LONGREG_BASE + 0x35)
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#define MRF24J40_ASSOEADR6 (MRF24J40_LONGREG_BASE + 0x36)
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#define MRF24J40_ASSOEADR7 (MRF24J40_LONGREG_BASE + 0x37)
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#define MRF24J40_ASSOSADR0 (MRF24J40_LONGREG_BASE + 0x38)
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#define MRF24J40_ASSOSADR1 (MRF24J40_LONGREG_BASE + 0x39)
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#define MRF24J40_UPNONCE0 (MRF24J40_LONGREG_BASE + 0x40)
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#define MRF24J40_UPNONCE1 (MRF24J40_LONGREG_BASE + 0x41)
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#define MRF24J40_UPNONCE2 (MRF24J40_LONGREG_BASE + 0x42)
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#define MRF24J40_UPNONCE3 (MRF24J40_LONGREG_BASE + 0x43)
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#define MRF24J40_UPNONCE4 (MRF24J40_LONGREG_BASE + 0x44)
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#define MRF24J40_UPNONCE5 (MRF24J40_LONGREG_BASE + 0x45)
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#define MRF24J40_UPNONCE6 (MRF24J40_LONGREG_BASE + 0x46)
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#define MRF24J40_UPNONCE7 (MRF24J40_LONGREG_BASE + 0x47)
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#define MRF24J40_UPNONCE8 (MRF24J40_LONGREG_BASE + 0x48)
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#define MRF24J40_UPNONCE9 (MRF24J40_LONGREG_BASE + 0x49)
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#define MRF24J40_UPNONCE10 (MRF24J40_LONGREG_BASE + 0x4A)
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#define MRF24J40_UPNONCE11 (MRF24J40_LONGREG_BASE + 0x4B)
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#define MRF24J40_UPNONCE12 (MRF24J40_LONGREG_BASE + 0x4C)
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/* INTSTAT bits */
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#define MRF24J40_INTSTAT_TXNIF (1 << 0)
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#define MRF24J40_INTSTAT_TXG1IF (1 << 1)
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#define MRF24J40_INTSTAT_TXG2IF (1 << 2)
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#define MRF24J40_INTSTAT_RXIF (1 << 3)
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#define MRF24J40_INTSTAT_SECIF (1 << 4)
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#define MRF24J40_INTSTAT_HSYMTMRIF (1 << 5)
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#define MRF24J40_INTSTAT_WAKEIF (1 << 6)
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#define MRF24J40_INTSTAT_SLPIF (1 << 7)
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/* RXMCR bits */
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#define MRF24J40_RXMCR_PROMI (1 << 0) /* Enable promisc mode (rx all valid packets) */
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#define MRF24J40_RXMCR_ERRPKT 0x02 /* Do not check CRC */
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#define MRF24J40_RXMCR_COORD 0x04 /* Enable coordinator mode ??? DIFFERENCE ??? - not used in datasheet! */
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#define MRF24J40_RXMCR_PANCOORD 0x08 /* Enable PAN coordinator mode ??? DIFFERENCE ??? */
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#define MRF24J40_RXMCR_NOACKRSP 0x20 /* Enable auto ACK when a packet is rxed */
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/* TXMCR bits */
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#define MRF24J40_TXMCR_CSMABF0 (1 << 0)
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#define MRF24J40_TXMCR_CSMABF1 0x02
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#define MRF24J40_TXMCR_CSMABF2 0x04
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#define MRF24J40_TXMCR_MACMINBE0 0x08
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#define MRF24J40_TXMCR_MACMINBE1 0x10
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#define MRF24J40_TXMCR_SLOTTED 0x20
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#define MRF24J40_TXMCR_BATLIFEXT 0x40
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#define MRF24J40_TXMCR_NOCSMA 0x80
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/* ACKTMOUT bits */
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#define MRF24J40_ACKTMOUT_MAWD 0xEF
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#define MRF24J40_ACKTMOUT_DRPACK 0x80
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/* INTCON bits */
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#define MRF24J40_INTCON_SLPIE 0x80
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#define MRF24J40_INTCON_WAKEIE 0x40
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#define MRF24J40_INTCON_HSYMTMRIE 0x20
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#define MRF24J40_INTCON_SECIE 0x10
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#define MRF24J40_INTCON_RXIE 0x08
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#define MRF24J40_INTCON_TXG2IE 0x04
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#define MRF24J40_INTCON_TXG1IE 0x02
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#define MRF24J40_INTCON_TXNIE (1 << 0)
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/* BBREG1 bits */
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#define MRF24J40_BBREG1_RXDECINV 0x04 /* Enable/Disable packet reception */
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/* BBREG2 bits */
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#define MRF24J40_BBREG2_CCAMODE_ED 0x80
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#define MRF24J40_BBREG2_CCAMODE_CS 0x40
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/* TXNCON bits */
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#define MRF24J40_TXNCON_TXNTRIG (1 << 0) /* Trigger packet tx, automatically cleared */
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#define MRF24J40_TXNCON_TXNSECEN 0x02 /* Enable security */
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#define MRF24J40_TXNCON_TXNACKREQ 0x04 /* An ACK is requested for this pkt */
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#define MRF24J40_TXNCON_INDIRECT 0x08 /* Activate indirect tx bit (for coordinators) */
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#define MRF24J40_TXNCON_FPSTAT 0x10 /* Status of the frame pending big in txed acks */
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/* TXSTAT bits */
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#define MRF24J40_TXSTAT_TXNSTAT (1 << 0)
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#define MRF24J40_TXSTAT_TXG1STAT (1 << 1)
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#define MRF24J40_TXSTAT_TXG2STAT (1 << 2)
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#define MRF24J40_TXSTAT_CCAFAIL (1 << 5)
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#define MRF24J40_TXSTAT_X_SHIFT 6
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#define MRF24J40_TXSTAT_X_MASK (3 << MRF24J40_TXSTAT_X_SHIFT)
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/* TXBCON0 bits */
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#define MRF24J40_TXBCON0_TXBTRIG 0x01
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#define MRF24J40_TXBCON0_TXBSECEN 0x02
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/* TXBCON1 bits */
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#define MRF24J40_TXBCON1_RSSINUM 0x30
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#define MRF24J40_TXBCON1_NWU_BCN 0x40
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#define MRF24J40_TXBCON1_TXBMSK 0x80
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/* WAKECON bits */
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#define MRF24J40_WAKECON_INTL 0x3F
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#define MRF24J40_WAKECON_REGWAKE 0x40
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#define MRF24J40_WAKECON_IMMWAKE 0x80
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/* WAKECON bits */
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#define MRF24J40_WAKECON_INTL 0x3F
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#define MRF24J40_WAKECON_REGWAKE 0x40
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#define MRF24J40_WAKECON_IMMWAKE 0x80
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/* ESLOTG1 bits */
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#define MRF24J40_ESLOTG1_CAP 0x0F
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#define MRF24J40_ESLOTG1_GTS1 0xF0
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/* SLPCAL2 bits */
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#define MRF24J40_SLPCAL2_SLPCAL 0x0F
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#define MRF24J40_SLPCAL2_SLPCALEN 0x10
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#define MRF24J40_SLPCAL2_SLPCALRDY 0x80
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/* RFCON7 bits */
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#define MRF24J40_RFCON7_SEL_32KHZ 0x40
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#define MRF24J40_RFCON7_SEL_100KHZ 0x80
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/* SLPACK bits */
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#define MRF24J40_SLPACK_WAKECNT0_6 0x7F
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#define MRF24J40_SLPACK_SLPACK 0x80
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/* RXFLUSH bits */
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#define MRF24J40_RXFLUSH_RXFLUSH 0x01
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#define MRF24J40_RXFLUSH_BCNONLY 0x02
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#define MRF24J40_RXFLUSH_DATAONLY 0x04
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#define MRF24J40_RXFLUSH_CMDONLY 0x08
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#define MRF24J40_RXFLUSH_WAKEPAD 0x20
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#define MRF24J40_RXFLUSH_WAKEPOL 0x40
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||
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#define MRF24J40_RXFLUSH_SHIFT_RXFLUSH 0
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||
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#define MRF24J40_RXFLUSH_SHIFT_BCNONLY 1
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||
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#define MRF24J40_RXFLUSH_SHIFT_DATAONLY 2
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||
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#define MRF24J40_RXFLUSH_SHIFT_CMDONLY 3
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||
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#define MRF24J40_RXFLUSH_SHIFT_WAKEPAD 5
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||
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#define MRF24J40_RXFLUSH_SHIFT_WAKEPOL 6
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