2018-04-04 18:57:36 +02:00
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/****************************************************************************
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* drivers/1wire/ds28e17.c
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*
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2021-11-15 08:04:55 +01:00
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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2018-04-04 18:57:36 +02:00
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*
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2021-11-15 08:04:55 +01:00
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* http://www.apache.org/licenses/LICENSE-2.0
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2018-04-04 18:57:36 +02:00
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*
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2021-11-15 08:04:55 +01:00
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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2018-04-04 18:57:36 +02:00
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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2021-05-18 08:59:14 +02:00
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#include <assert.h>
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2018-04-04 18:57:36 +02:00
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#include <errno.h>
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#include <debug.h>
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#include <string.h>
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#include <nuttx/kmalloc.h>
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#include <nuttx/i2c/i2c_master.h>
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2021-04-08 18:21:35 +02:00
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#include <nuttx/1wire/1wire_master.h>
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#include <nuttx/1wire/1wire_crc.h>
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#include <nuttx/1wire/1wire.h>
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2018-04-04 18:57:36 +02:00
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#include <nuttx/1wire/ds28e17.h>
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#include "1wire_internal.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#ifndef CONFIG_DS28E17_I2C_FREQUENCY
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# define CONFIG_DS28E17_I2C_FREQUENCY 400000
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#endif
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/* DS28E17 device 1-Wire family ID */
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#define DS_FAMILY 0x19
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/* DS28E17 device I2C commands */
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#define DS_WRITE_DATA_WITH_STOP 0x4b
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#define DS_WRITE_DATA_NO_STOP 0x5a
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#define DS_WRITE_DATA_ONLY 0x69
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#define DS_WRITE_DATA_ONLY_WITH_STOP 0x78
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#define DS_READ_DATA_WITH_STOP 0x87
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#define DS_WRITE_READ_DATA_WITH_STOP 0x2d
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#define DS_WRITE_CONFIGURATION 0xd2
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#define DS_READ_CONFIGURATION 0xe1
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#define DS_ENABLE_SLEEP_MODE 0x1e
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#define DS_READ_DEVICE_REVISION 0xc4
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/* DS28E17 status bits */
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#define DS_STATUS_CRC 0x01
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#define DS_STATUS_ADDRESS 0x02
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#define DS_STATUS_START 0x08
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/* Maximum number of I2C bytes to transfer within one CRC16 protected onewire
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* command (same for either read and write).
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*/
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#define DS_DATA_LIMIT 255
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/* Default I2C frequency to use when DS28E17 is detected. */
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#define DS_DEFAULT_FREQUENCY CONFIG_DS28E17_I2C_FREQUENCY
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/* Default I2C stretch value. */
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#define DS_DEFAULT_STRETCH 1
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/* How many times to retry check for chip busy condition vanishing. */
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#define DS_BUSYWAIT_RETRIES 500
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/****************************************************************************
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* Private Types
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****************************************************************************/
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struct ds28e17_dev_s /* Must be cast-compatible with onewire_master_s */
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{
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FAR struct onewire_dev_s *dev; /* 1-wire interface */
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};
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/* I2C Device, Instance */
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struct ds_i2c_inst_s /* Must be cast-compatible with i2c_master_s */
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{
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FAR const struct i2c_ops_s *ops; /* Standard I2C operations */
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/* 1-wire data */
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FAR struct onewire_master_s *master; /* 1-wire bus master */
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FAR struct onewire_slave_s slave; /* Our slave data on 1-wire bus */
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/* I2C data */
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uint32_t frequency; /* Current I2C frequency */
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uint8_t stretch; /* Current I2C stretch value */
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};
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/****************************************************************************
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* Private Function Prototypes
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****************************************************************************/
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2021-04-08 19:12:10 +02:00
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#ifdef CONFIG_I2C_RESET
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2018-04-04 18:57:36 +02:00
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static int ds_i2c_reset(FAR struct i2c_master_s *i2cdev);
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2021-04-08 19:12:10 +02:00
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#endif
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2018-04-04 18:57:36 +02:00
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static int ds_i2c_transfer(FAR struct i2c_master_s *i2cdev,
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FAR struct i2c_msg_s *msgs, int count);
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/* Device Structures, Instantiation */
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static const struct i2c_ops_s ds_i2c_ops =
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{
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2022-03-26 21:51:22 +01:00
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ds_i2c_transfer
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2018-04-04 18:57:36 +02:00
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#ifdef CONFIG_I2C_RESET
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2022-03-26 21:51:22 +01:00
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, ds_i2c_reset
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2018-04-04 18:57:36 +02:00
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#endif
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};
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: ds_i2c_sem_wait
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*
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* Description:
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* Take the exclusive access, waiting as necessary
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*
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****************************************************************************/
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2020-03-31 23:19:07 +02:00
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static inline int ds_i2c_sem_wait(FAR struct i2c_master_s *i2cdev)
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2018-04-04 18:57:36 +02:00
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{
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FAR struct ds_i2c_inst_s *inst = (FAR struct ds_i2c_inst_s *)i2cdev;
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FAR struct onewire_master_s *master = inst->master;
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return onewire_sem_wait(master);
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}
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/****************************************************************************
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* Name: ds_i2c_sem_post
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*
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* Description:
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* Release the mutual exclusion semaphore
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*
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****************************************************************************/
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static inline void ds_i2c_sem_post(FAR struct i2c_master_s *i2cdev)
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{
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FAR struct ds_i2c_inst_s *inst = (FAR struct ds_i2c_inst_s *)i2cdev;
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FAR struct onewire_master_s *master = inst->master;
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onewire_sem_post(master);
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}
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static int ds_error(uint8_t buf[])
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{
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/* Warnings */
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if (buf[0] & DS_STATUS_CRC)
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{
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i2cwarn("crc16 match failed\n");
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}
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if ((buf[0] & (DS_STATUS_CRC | DS_STATUS_ADDRESS)) == 0 && buf[1] != 0)
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{
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i2cwarn("I2C short write, no ack for %d bytes\n", buf[1]);
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}
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/* Error conditions */
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if (buf[0] & DS_STATUS_ADDRESS)
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{
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i2cerr("I2C device not responding\n");
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return -ENXIO;
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}
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2020-03-31 23:19:07 +02:00
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2018-04-04 18:57:36 +02:00
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if (buf[0] & DS_STATUS_START)
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{
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i2cerr("I2C status start\n");
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return -EAGAIN;
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}
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2020-03-31 23:19:07 +02:00
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2018-04-04 18:57:36 +02:00
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if (buf[0] != 0 || buf[1] != 0)
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{
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i2cerr("I2C IO error\n");
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return -EIO;
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}
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return OK;
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}
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static inline int ds_busywait_time(FAR struct ds_i2c_inst_s *inst)
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{
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int d;
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/* Return busywait time (us) for I2C speeds 100 kHz, 400 kHz
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* and 900 kHz, adjusted with current stretch value.
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*/
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switch (inst->frequency)
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{
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case 100000:
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d = 90;
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break;
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case 400000:
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default:
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d = 23;
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break;
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case 900000:
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d = 10;
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break;
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}
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return d * inst->stretch;
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}
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static int ds_busywait(FAR struct ds_i2c_inst_s *inst, size_t length)
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{
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FAR struct onewire_master_s *master = inst->master;
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int retries = DS_BUSYWAIT_RETRIES;
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int delay;
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int ret;
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uint8_t bit = 1;
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/* Calculate delay time from current I2C settings. */
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delay = ds_busywait_time(inst);
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do
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{
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ret = ONEWIRE_READBIT(master->dev, &bit);
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if (ret < 0)
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{
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i2cerr("ERROR: ONEWIRE_READBIT failed\n");
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return ret;
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}
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if (bit == 0)
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{
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return OK;
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}
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if (retries == DS_BUSYWAIT_RETRIES)
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{
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/* First time, after checking bit once, do a big delay
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* for I2C to process all bytes in message.
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*/
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up_udelay(delay * length);
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}
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else
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{
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/* Otherwise, wait for one byte duration. */
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up_udelay(delay);
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}
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2020-03-31 23:19:07 +02:00
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}
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while (retries-- > 0);
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2018-04-04 18:57:36 +02:00
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i2cwarn("busywait timeout\n");
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return -ETIMEDOUT;
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}
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/****************************************************************************
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* Name: ds_i2c_read
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*
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* Description:
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* Read data from I2C slave.
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*
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****************************************************************************/
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static int ds_i2c_read(FAR struct ds_i2c_inst_s *inst, uint16_t i2c_addr,
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FAR uint8_t *buffer, ssize_t length)
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{
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FAR struct onewire_master_s *master = inst->master;
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uint16_t crc;
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int ret;
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uint8_t buf[5];
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if (length <= 0)
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{
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return -EINVAL;
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}
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if (length > DS_DATA_LIMIT)
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{
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i2cerr("ERROR: reading too many bytes!\n");
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return -EINVAL;
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}
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/* Send command to DS28E17. */
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buf[0] = DS_READ_DATA_WITH_STOP;
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buf[1] = i2c_addr << 1 | 0x01;
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buf[2] = length;
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crc = onewire_crc16(buf, 3, 0);
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buf[3] = ~(crc & 0xff);
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buf[4] = ~((crc >> 8) & 0xff);
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ret = ONEWIRE_WRITE(master->dev, buf, 5);
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if (ret < 0)
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{
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return ret;
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}
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/* Wait busy indication to vanish. */
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ret = ds_busywait(inst, length + 1);
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if (ret < 0)
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{
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return ret;
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}
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/* Read status from DS28E17. */
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ret = ONEWIRE_READ(master->dev, buf, 1);
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buf[1] = 0;
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/* Check error conditions. */
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ret = ds_error(buf);
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if (ret < 0)
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{
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return ret;
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}
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/* Read received I2C data from DS28E17. */
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return ONEWIRE_READ(master->dev, buffer, length);
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}
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/****************************************************************************
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* Name: ds_i2c_write
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*
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* Description:
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* Write data to I2C slave.
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*
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****************************************************************************/
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static int ds_i2c_write(FAR struct ds_i2c_inst_s *inst, uint16_t i2c_addr,
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FAR const uint8_t *buffer, ssize_t length, bool stop)
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{
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FAR struct onewire_master_s *master = inst->master;
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uint16_t crc;
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int ret;
|
2018-12-11 14:09:03 +01:00
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uint8_t buf[3];
|
2018-04-04 18:57:36 +02:00
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if (length <= 0)
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{
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return -EINVAL;
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}
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if (length > DS_DATA_LIMIT)
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{
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/* TODO: split big writes into multiple chunks. */
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i2cerr("ERROR: writing too many bytes!\n");
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return -EINVAL;
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}
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/* Write command header. */
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|
|
buf[0] = stop ? DS_WRITE_DATA_WITH_STOP : DS_WRITE_DATA_NO_STOP;
|
|
|
|
buf[1] = i2c_addr << 1;
|
|
|
|
buf[2] = length;
|
|
|
|
crc = onewire_crc16(buf, 3, 0);
|
|
|
|
|
|
|
|
ret = ONEWIRE_WRITE(master->dev, buf, 3);
|
|
|
|
if (ret < 0)
|
|
|
|
{
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Write payload I2C data to DS28E17. */
|
|
|
|
|
|
|
|
crc = onewire_crc16(buffer, length, crc);
|
|
|
|
|
|
|
|
ret = ONEWIRE_WRITE(master->dev, buffer, length);
|
|
|
|
if (ret < 0)
|
|
|
|
{
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Write checksum. */
|
|
|
|
|
|
|
|
buf[0] = ~(crc & 0xff);
|
|
|
|
buf[1] = ~((crc >> 8) & 0xff);
|
|
|
|
|
|
|
|
ret = ONEWIRE_WRITE(master->dev, buf, 2);
|
|
|
|
if (ret < 0)
|
|
|
|
{
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Wait busy indication to vanish. */
|
|
|
|
|
|
|
|
ret = ds_busywait(inst, length + 1);
|
|
|
|
if (ret < 0)
|
|
|
|
{
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Read status from DS28E17. */
|
|
|
|
|
|
|
|
ret = ONEWIRE_READ(master->dev, buf, 2);
|
|
|
|
if (ret < 0)
|
|
|
|
{
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Check error conditions. */
|
|
|
|
|
|
|
|
ret = ds_error(buf);
|
|
|
|
if (ret < 0)
|
|
|
|
{
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Return count of bytes written. */
|
|
|
|
|
|
|
|
return length;
|
|
|
|
}
|
|
|
|
|
2018-12-11 14:09:03 +01:00
|
|
|
/****************************************************************************
|
|
|
|
* Name: ds_i2c_write_read
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Write data to I2C slave and read from same address.
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
2020-03-31 23:19:07 +02:00
|
|
|
static int ds_i2c_write_read(FAR struct ds_i2c_inst_s *inst,
|
|
|
|
uint16_t i2c_addr,
|
2018-12-11 14:09:03 +01:00
|
|
|
FAR const uint8_t *wbuffer, ssize_t wlength,
|
|
|
|
FAR uint8_t *rbuffer, ssize_t rlength)
|
|
|
|
{
|
|
|
|
FAR struct onewire_master_s *master = inst->master;
|
|
|
|
uint16_t crc;
|
|
|
|
int ret;
|
|
|
|
uint8_t buf[3];
|
|
|
|
|
|
|
|
if (wlength <= 0 || rlength <= 0)
|
|
|
|
{
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (wlength > DS_DATA_LIMIT)
|
|
|
|
{
|
|
|
|
i2cerr("ERROR: writing too many bytes!\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (rlength > DS_DATA_LIMIT)
|
|
|
|
{
|
|
|
|
i2cerr("ERROR: reading too many bytes!\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Write command header. */
|
|
|
|
|
|
|
|
buf[0] = DS_WRITE_READ_DATA_WITH_STOP;
|
|
|
|
buf[1] = i2c_addr << 1;
|
|
|
|
buf[2] = wlength;
|
|
|
|
crc = onewire_crc16(buf, 3, 0);
|
|
|
|
|
|
|
|
ret = ONEWIRE_WRITE(master->dev, buf, 3);
|
|
|
|
if (ret < 0)
|
|
|
|
{
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Write payload I2C data to DS28E17. */
|
|
|
|
|
|
|
|
crc = onewire_crc16(wbuffer, wlength, crc);
|
|
|
|
|
|
|
|
ret = ONEWIRE_WRITE(master->dev, wbuffer, wlength);
|
|
|
|
if (ret < 0)
|
|
|
|
{
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Write read length and checksum. */
|
|
|
|
|
|
|
|
buf[0] = rlength;
|
|
|
|
crc = onewire_crc16(buf, 1, crc);
|
|
|
|
buf[1] = ~(crc & 0xff);
|
|
|
|
buf[2] = ~((crc >> 8) & 0xff);
|
|
|
|
|
|
|
|
ret = ONEWIRE_WRITE(master->dev, buf, 3);
|
|
|
|
if (ret < 0)
|
|
|
|
{
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Wait busy indication to vanish. */
|
|
|
|
|
|
|
|
ret = ds_busywait(inst, wlength + 1 + rlength + 1);
|
|
|
|
if (ret < 0)
|
|
|
|
{
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Read status from DS28E17. */
|
|
|
|
|
|
|
|
ret = ONEWIRE_READ(master->dev, buf, 2);
|
|
|
|
if (ret < 0)
|
|
|
|
{
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Check error conditions. */
|
|
|
|
|
|
|
|
ret = ds_error(buf);
|
|
|
|
if (ret < 0)
|
|
|
|
{
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Read received I2C data from DS28E17. */
|
|
|
|
|
|
|
|
return ONEWIRE_READ(master->dev, rbuffer, rlength);
|
|
|
|
}
|
|
|
|
|
2020-03-31 23:19:07 +02:00
|
|
|
static int ds_i2c_setfrequency(FAR struct ds_i2c_inst_s *inst,
|
|
|
|
uint32_t frequency)
|
2018-04-04 18:57:36 +02:00
|
|
|
{
|
|
|
|
FAR struct onewire_master_s *master = inst->master;
|
|
|
|
uint8_t buf[2];
|
|
|
|
int speed;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
switch (frequency)
|
|
|
|
{
|
|
|
|
case 100000:
|
|
|
|
speed = 0;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case 400000:
|
|
|
|
speed = 1;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case 900000:
|
|
|
|
speed = 2;
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
2021-04-08 19:12:10 +02:00
|
|
|
i2cerr("ERROR: bad I2C freq %lu\n", frequency);
|
2018-04-04 18:57:36 +02:00
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2021-04-08 19:12:10 +02:00
|
|
|
i2cinfo("Changing I2C freq %lu -> %lu\n", inst->frequency, frequency);
|
2018-04-04 18:57:36 +02:00
|
|
|
|
|
|
|
/* Select DS28E17 */
|
|
|
|
|
2021-04-08 19:12:10 +02:00
|
|
|
ret = onewire_reset_select(master, inst->slave.romcode);
|
2018-04-04 18:57:36 +02:00
|
|
|
if (ret < 0)
|
|
|
|
{
|
|
|
|
i2cerr("ERROR: cannot change I2C freq\n");
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Write new speed to device */
|
|
|
|
|
|
|
|
buf[0] = DS_WRITE_CONFIGURATION;
|
|
|
|
buf[1] = speed;
|
|
|
|
|
|
|
|
ret = ONEWIRE_WRITE(master->dev, buf, 2);
|
|
|
|
if (ret < 0)
|
|
|
|
{
|
|
|
|
i2cerr("ERROR: cannot change I2C freq\n");
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
inst->frequency = frequency;
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: ds_i2c_process
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Common I2C transfer logic
|
|
|
|
*
|
|
|
|
* Initiates a master mode transaction on the I2C bus to transfer the
|
|
|
|
* provided messages to and from the slave devices.
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
static int ds_i2c_process(FAR struct i2c_master_s *i2cdev,
|
|
|
|
FAR struct i2c_msg_s *msgs, int count)
|
|
|
|
{
|
|
|
|
FAR struct ds_i2c_inst_s *inst = (FAR struct ds_i2c_inst_s *)i2cdev;
|
|
|
|
FAR struct onewire_master_s *master = inst->master;
|
|
|
|
int ret;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
/* Check from first message only, if we want to change I2C frequency. */
|
|
|
|
|
|
|
|
if (inst->frequency != msgs[0].frequency)
|
|
|
|
{
|
|
|
|
ds_i2c_setfrequency(inst, msgs[0].frequency);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Select DS28E17 */
|
|
|
|
|
2021-04-08 19:12:10 +02:00
|
|
|
i = onewire_reset_select(master, inst->slave.romcode);
|
2018-04-04 18:57:36 +02:00
|
|
|
if (i < 0)
|
|
|
|
{
|
|
|
|
goto errout;
|
|
|
|
}
|
|
|
|
|
|
|
|
while (i < count)
|
|
|
|
{
|
2018-12-11 14:09:03 +01:00
|
|
|
/* First we try to use DS_WRITE_READ_DATA_WITH_STOP to optimize
|
|
|
|
* the common case of write followed by read to a same address.
|
2018-04-04 18:57:36 +02:00
|
|
|
*/
|
|
|
|
|
2020-03-31 23:19:07 +02:00
|
|
|
if (i < count - 1 && msgs[i].addr == msgs[i + 1].addr &&
|
2018-12-11 14:09:03 +01:00
|
|
|
(msgs[i].flags & I2C_M_READ) == 0 &&
|
2020-03-31 23:19:07 +02:00
|
|
|
(msgs[i + 1].flags & I2C_M_READ))
|
2018-12-11 14:09:03 +01:00
|
|
|
{
|
|
|
|
/* Write-read combined transfer. */
|
|
|
|
|
|
|
|
ret = ds_i2c_write_read(inst, msgs[i].addr,
|
|
|
|
msgs[i].buffer, msgs[i].length,
|
2020-03-31 23:19:07 +02:00
|
|
|
msgs[i + 1].buffer, msgs[i + 1].length);
|
2018-12-11 14:09:03 +01:00
|
|
|
if (ret < 0)
|
|
|
|
{
|
|
|
|
i = ret;
|
|
|
|
goto errout;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* We processed two messages here. */
|
|
|
|
|
|
|
|
i += 2;
|
|
|
|
}
|
|
|
|
else if (msgs[i].flags & I2C_M_READ)
|
2018-04-04 18:57:36 +02:00
|
|
|
{
|
|
|
|
/* Read transfer. */
|
|
|
|
|
2020-03-31 23:19:07 +02:00
|
|
|
ret = ds_i2c_read(inst, msgs[i].addr, msgs[i].buffer,
|
|
|
|
msgs[i].length);
|
2018-04-04 18:57:36 +02:00
|
|
|
if (ret < 0)
|
|
|
|
{
|
|
|
|
i = ret;
|
|
|
|
goto errout;
|
|
|
|
}
|
2018-12-11 14:09:03 +01:00
|
|
|
|
|
|
|
i++;
|
2018-04-04 18:57:36 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* Write transfer. Stop condition only for last transfer. */
|
|
|
|
|
2020-03-31 23:19:07 +02:00
|
|
|
ret = ds_i2c_write(inst, msgs[i].addr, msgs[i].buffer,
|
|
|
|
msgs[i].length, i == (count - 1));
|
2018-04-04 18:57:36 +02:00
|
|
|
if (ret < 0)
|
|
|
|
{
|
|
|
|
i = ret;
|
|
|
|
goto errout;
|
|
|
|
}
|
2018-12-11 14:09:03 +01:00
|
|
|
|
|
|
|
i++;
|
2018-04-04 18:57:36 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Any more messages to process? */
|
|
|
|
|
|
|
|
if (i < count)
|
|
|
|
{
|
2020-03-31 23:19:07 +02:00
|
|
|
/* Yes. Resume to same DS28E17.
|
|
|
|
* Oddness: Skip-ROM does not set RS-bit needed by resume.
|
|
|
|
*/
|
2018-04-04 18:57:36 +02:00
|
|
|
|
|
|
|
if (master->nslaves > 1)
|
|
|
|
{
|
|
|
|
ret = onewire_reset_resume(master);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2021-04-08 19:12:10 +02:00
|
|
|
ret = onewire_reset_select(master, inst->slave.romcode);
|
2018-04-04 18:57:36 +02:00
|
|
|
}
|
2020-03-31 23:19:07 +02:00
|
|
|
|
2018-04-04 18:57:36 +02:00
|
|
|
if (ret < 0)
|
|
|
|
{
|
|
|
|
i = ret;
|
|
|
|
goto errout;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
errout:
|
|
|
|
return i;
|
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: ds_i2c_reset
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Reset an I2C bus
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
#ifdef CONFIG_I2C_RESET
|
|
|
|
static int ds_i2c_reset(FAR struct i2c_master_s *i2cdev)
|
|
|
|
{
|
|
|
|
FAR struct ds_i2c_inst_s *inst = (FAR struct ds_i2c_inst_s *)i2cdev;
|
|
|
|
FAR struct onewire_master_s *master = inst->master;
|
|
|
|
int ret;
|
|
|
|
|
2020-03-31 23:19:07 +02:00
|
|
|
ret = ds_i2c_sem_wait(i2cdev);
|
|
|
|
if (ret < 0)
|
|
|
|
{
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2018-04-04 18:57:36 +02:00
|
|
|
ret = ONEWIRE_RESET(master->dev);
|
|
|
|
ds_i2c_sem_post(i2cdev);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: ds_i2c_transfer
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Generic I2C transfer function
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
static int ds_i2c_transfer(FAR struct i2c_master_s *i2cdev,
|
|
|
|
FAR struct i2c_msg_s *msgs,
|
|
|
|
int count)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
2020-03-31 23:19:07 +02:00
|
|
|
ret = ds_i2c_sem_wait(i2cdev);
|
|
|
|
if (ret < 0)
|
|
|
|
{
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2018-04-04 18:57:36 +02:00
|
|
|
ret = ds_i2c_process(i2cdev, msgs, count);
|
|
|
|
ds_i2c_sem_post(i2cdev);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: ds28e17_selftest
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
static int ds28e17_selftest(FAR struct ds_i2c_inst_s *inst)
|
|
|
|
{
|
|
|
|
FAR struct onewire_master_s *master = inst->master;
|
2020-03-31 23:19:07 +02:00
|
|
|
uint8_t txbuf[] =
|
|
|
|
{
|
|
|
|
ONEWIRE_CMD_READ_ROM
|
|
|
|
};
|
|
|
|
|
|
|
|
uint8_t rxbuf[8] =
|
|
|
|
{
|
|
|
|
0
|
|
|
|
};
|
|
|
|
|
2018-04-04 18:57:36 +02:00
|
|
|
uint64_t rom;
|
|
|
|
uint8_t crc;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
/* Read ROM-code of single connected slave and
|
|
|
|
* check its checksum.
|
|
|
|
*/
|
|
|
|
|
|
|
|
ret = ONEWIRE_RESET(master->dev);
|
|
|
|
if (ret < 0)
|
|
|
|
{
|
|
|
|
i2cerr("ERROR: ONEWIRE_RESET failed: %d\n", ret);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = ONEWIRE_WRITE(master->dev, txbuf, sizeof(txbuf));
|
|
|
|
if (ret < 0)
|
|
|
|
{
|
|
|
|
i2cerr("ERROR: ONEWIRE_WRITE failed: %d\n", ret);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = ONEWIRE_READ(master->dev, rxbuf, sizeof(rxbuf));
|
|
|
|
if (ret < 0)
|
|
|
|
{
|
|
|
|
i2cerr("ERROR: ONEWIRE_READ failed: %d\n", ret);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
#ifdef CONFIG_DEBUG_I2C_INFO
|
|
|
|
lib_dumpbuffer("ds28e17_selftest: rxbuf", rxbuf, sizeof(rxbuf));
|
|
|
|
|
|
|
|
#endif
|
|
|
|
memcpy(&rom, rxbuf, 8);
|
|
|
|
i2cinfo("recv rom: 0x%llx\n", rom);
|
|
|
|
|
|
|
|
crc = onewire_crc8(rxbuf, sizeof(rxbuf)-1);
|
|
|
|
i2cinfo("crc8=%d, recv crc8=%d\n", crc, (int)rxbuf[7]);
|
|
|
|
if (crc != rxbuf[7])
|
|
|
|
{
|
|
|
|
i2cerr("ERROR: crc8 does not match!\n");
|
|
|
|
ret = -EIO;
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Public Functions
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: ds28e17_search
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Search all DS28E17 devices from a 1-wire network.
|
|
|
|
*
|
|
|
|
* Input Parameters:
|
|
|
|
* priv - Pointer to the associated DS28E17
|
|
|
|
* cb_search - Callback to call on each device found
|
|
|
|
* arg - Argument passed to cb_search
|
|
|
|
*
|
|
|
|
* Return Value:
|
|
|
|
* Number of DS28E17 devices present.
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
int ds28e17_search(FAR struct ds28e17_dev_s *priv,
|
2020-03-31 23:19:07 +02:00
|
|
|
void (*cb_search)(int family,
|
|
|
|
uint64_t romcode,
|
|
|
|
void *arg),
|
2018-04-04 18:57:36 +02:00
|
|
|
void *arg)
|
|
|
|
{
|
|
|
|
FAR struct onewire_master_s *master = (FAR struct onewire_master_s *)priv;
|
|
|
|
|
|
|
|
DEBUGASSERT(master != NULL && cb_search != NULL);
|
|
|
|
|
2021-04-08 19:12:10 +02:00
|
|
|
return onewire_search(master, DS_FAMILY, false, cb_search, arg);
|
2018-04-04 18:57:36 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: ds28e17_lower_half
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Initialize the lower half of the DS28E17 by creating a i2c_master_s
|
|
|
|
* for the virtual i2c master and link it to the associated DS28E17 and
|
|
|
|
* its port.
|
|
|
|
*
|
|
|
|
* Input Parameters:
|
|
|
|
* dev - Pointer to the associated DS28E17
|
|
|
|
* romcode - The unique 64-bit address in 1-wire network.
|
|
|
|
* Use zero for skip-ROM mode.
|
|
|
|
*
|
|
|
|
* Returned Value:
|
|
|
|
* i2c device instance; NULL on failure.
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
FAR struct i2c_master_s *
|
|
|
|
ds28e17_lower_half(FAR struct ds28e17_dev_s *priv, uint64_t romcode)
|
|
|
|
{
|
|
|
|
FAR struct ds_i2c_inst_s *inst; /* device, single instance */
|
|
|
|
FAR struct onewire_master_s *master = (FAR struct onewire_master_s *)priv;
|
2020-03-31 23:19:07 +02:00
|
|
|
int ret;
|
2018-04-04 18:57:36 +02:00
|
|
|
|
|
|
|
DEBUGASSERT(master != NULL);
|
|
|
|
|
|
|
|
/* Allocate instance */
|
|
|
|
|
2018-04-24 15:21:02 +02:00
|
|
|
inst = kmm_zalloc(sizeof(struct ds_i2c_inst_s));
|
2018-04-04 18:57:36 +02:00
|
|
|
if (inst == NULL)
|
|
|
|
{
|
|
|
|
i2cerr("ERROR: Failed to allocate instance\n");
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Initialize instance */
|
|
|
|
|
|
|
|
inst->ops = &ds_i2c_ops;
|
|
|
|
inst->master = master;
|
|
|
|
inst->frequency = 400000; /* power-on frequency */
|
|
|
|
inst->stretch = DS_DEFAULT_STRETCH;
|
2018-04-24 15:21:02 +02:00
|
|
|
inst->slave.romcode = romcode;
|
2018-04-04 18:57:36 +02:00
|
|
|
|
|
|
|
/* We need a recursive lock as this may be called from a search callback. */
|
|
|
|
|
2020-03-31 23:19:07 +02:00
|
|
|
ret = onewire_sem_wait(master);
|
|
|
|
if (ret < 0)
|
|
|
|
{
|
|
|
|
kmm_free(inst);
|
|
|
|
i2cerr("ERROR: Failed to acquire lock\n");
|
|
|
|
return NULL;
|
|
|
|
}
|
2018-04-04 18:57:36 +02:00
|
|
|
|
|
|
|
if (onewire_addslave(master, &inst->slave) < 0)
|
|
|
|
{
|
|
|
|
kmm_free(inst);
|
|
|
|
i2cerr("ERROR: Failed to add slave\n");
|
|
|
|
onewire_sem_post(master);
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Should default speed be different from DS28E17 power-on frequency? */
|
|
|
|
|
|
|
|
if (inst->frequency != DS_DEFAULT_FREQUENCY)
|
|
|
|
{
|
|
|
|
ds_i2c_setfrequency(inst, DS_DEFAULT_FREQUENCY);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* TODO: better selftest */
|
|
|
|
|
|
|
|
if (master->maxslaves == 1)
|
|
|
|
{
|
|
|
|
ds28e17_selftest(inst);
|
|
|
|
}
|
|
|
|
|
|
|
|
onewire_sem_post(master);
|
|
|
|
return (struct i2c_master_s *)inst;
|
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: ds28e17_lower_half_unregister
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Put back the lower half of the DS28E17.
|
|
|
|
*
|
|
|
|
* Input Parameters:
|
|
|
|
* priv - Pointer to the associated DS28E17
|
|
|
|
* i2cdev - i2c device instance from ds28e17_lower_half()
|
|
|
|
*
|
|
|
|
* Returned Value:
|
|
|
|
* Zero on success; a negated errno value on failure.
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
int ds28e17_lower_half_unregister(FAR struct ds28e17_dev_s *priv,
|
|
|
|
FAR struct i2c_master_s *i2cdev)
|
|
|
|
{
|
|
|
|
FAR struct ds_i2c_inst_s *inst = (FAR struct ds_i2c_inst_s *)i2cdev;
|
|
|
|
FAR struct onewire_master_s *master = inst->master;
|
|
|
|
int ret;
|
|
|
|
|
2020-03-31 23:19:07 +02:00
|
|
|
ret = onewire_sem_wait(master);
|
|
|
|
if (ret < 0)
|
|
|
|
{
|
|
|
|
return ret;
|
|
|
|
}
|
2018-04-04 18:57:36 +02:00
|
|
|
|
|
|
|
ret = onewire_removeslave(master, &inst->slave);
|
|
|
|
if (ret < 0)
|
|
|
|
{
|
|
|
|
kmm_free(inst);
|
|
|
|
i2cerr("ERROR: Failed to remove slave\n");
|
|
|
|
onewire_sem_post(master);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
kmm_free(inst);
|
|
|
|
onewire_sem_post(master);
|
|
|
|
|
|
|
|
return OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: ds28e17_initialize
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Returns a common DS28E17 device from 1-wire lower half device
|
|
|
|
*
|
|
|
|
* Input Parameters:
|
|
|
|
* dev - The allocated 1-wire lower half
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
FAR struct ds28e17_dev_s *ds28e17_initialize(FAR struct onewire_dev_s *dev)
|
|
|
|
{
|
|
|
|
FAR struct onewire_master_s *priv;
|
|
|
|
|
|
|
|
priv = onewire_initialize(dev, DS_DEFAULT_MAXSLAVES);
|
|
|
|
|
|
|
|
/* We do not have our own data fields so just cast it. */
|
|
|
|
|
|
|
|
return (FAR struct ds28e17_dev_s *)priv;
|
|
|
|
}
|