2016-01-15 19:17:30 +01:00
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/****************************************************************************
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2021-03-08 22:39:04 +01:00
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* boards/arm/lpc43xx/lpc4370-link2/include/board.h
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2016-01-15 19:17:30 +01:00
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*
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2021-03-17 18:14:12 +01:00
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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2016-01-15 19:17:30 +01:00
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*
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2021-03-17 18:14:12 +01:00
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* http://www.apache.org/licenses/LICENSE-2.0
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2016-01-15 19:17:30 +01:00
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*
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2021-03-17 18:14:12 +01:00
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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2016-01-15 19:17:30 +01:00
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*
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****************************************************************************/
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2022-01-15 03:44:35 +01:00
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#ifndef __BOARDS_ARM_LPC43XX_LPC4370_LINK2_INCLUDE_BOARD_H
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#define __BOARDS_ARM_LPC43XX_LPC4370_LINK2_INCLUDE_BOARD_H
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2015-09-29 15:53:49 +02:00
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdbool.h>
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2016-07-22 22:55:39 +02:00
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#if defined(CONFIG_ARCH_IRQBUTTONS) && defined(CONFIG_LPC43_GPIO_IRQ)
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2015-09-29 15:53:49 +02:00
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# include <nuttx/irq.h>
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#endif
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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2020-06-06 15:16:53 +02:00
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/* Clocking *****************************************************************/
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2019-08-14 14:34:18 +02:00
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2015-09-29 15:53:49 +02:00
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/* NOTE: The following definitions require lpc43_cgu.h. It is not included
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* here because the including C file may not have that file in its include
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* path.
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*
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* The Xplorer board has four crystals on board:
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*
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* Y1 - RTC 32.768 MHz oscillator input,
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* Y2 - 24.576 MHz input to the UDA 1380 audio codec,
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* Y3 - 12.000 MHz LPC43xx crystal oscillator input
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* Y4 - 50 MHz input for Ethernet
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*/
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#define BOARD_XTAL_FREQUENCY (12000000) /* XTAL oscillator frequency (Y3) */
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#define BOARD_RTCCLK_FREQUENCY (32768) /* RTC oscillator frequency (Y1) */
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#define BOARD_INTRCOSC_FREQUENCY (4000000) /* Internal RC oscillator frequency */
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/* Integer and direct modes are supported:
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*
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* In integer mode (Fclkout < 156000000):
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* Fclkin = BOARD_XTAL_FREQUENCY
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* Fclkout = Msel * FClkin / Nsel
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* Fcco = 2 * Psel * Fclkout
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* In direct mode (Fclkout > 156000000):
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* Fclkin = BOARD_XTAL_FREQUENCY
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* Fclkout = Msel * FClkin / Nsel
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* Fcco = Fclkout
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*/
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#ifdef CONFIG_LPC43_72MHz
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/* NOTE: At 72MHz, the calibrated value of CONFIG_BOARD_LOOPSPERMSEC was
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* determined to be:
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*
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* CONFIG_BOARD_LOOPSPERMSEC=7191
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*
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* executing from SRAM.
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*/
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/* Final clocking (Integer mode with no ramp-up)
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*
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* Fclkout = 6 * 12MHz / 1 = 72MHz
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* Fcco = 2 * 2 * 72MHz = 216MHz
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*/
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# define BOARD_PLL_MSEL (6) /* Msel = 6 */
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# define BOARD_PLL_NSEL (1) /* Nsel = 1 */
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# define BOARD_PLL_PSEL (2) /* Psel = 2 */
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# define BOARD_FCLKOUT_FREQUENCY (72000000) /* 6 * 12,000,000 / 1 */
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# define BOARD_FCCO_FREQUENCY (244000000) /* 2 * 2 * Fclkout */
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#else
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/* NOTE: At 72MHz, the calibrated value of CONFIG_BOARD_LOOPSPERMSEC was
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* determined to be:
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*
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* CONFIG_BOARD_LOOPSPERMSEC=18535
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*
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* executing from SRAM.
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*/
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/* Intermediate ramp-up clocking (Integer mode). If BOARD_PLL_RAMP_MSEL
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* is not defined, there will be no ramp-up.
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*
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* Fclkout = 9 * 12MHz / 1 = 108MHz
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* Fcco = 2 * 1 * 108MHz = 216MHz
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*/
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# define BOARD_PLL_RAMP_MSEL (9) /* Msel = 9 */
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# define BOARD_PLL_RAMP_NSEL (1) /* Nsel = 1 */
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# define BOARD_PLL_RAMP_PSEL (1) /* Psel = 1 */
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# define BOARD_RAMP_FCLKOUT (108000000) /* 9 * 12,000,000 / 1 */
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# define BOARD_RAMP_FCCO (216000000) /* 2 * 1 * Fclkout */
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/* Final clocking (Direct mode).
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*
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* Fclkout = 17 * 12MHz / 1 = 204MHz
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* Fcco = Fclockout = 204MHz
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*/
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# define BOARD_PLL_MSEL (17) /* Msel = 17 */
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# define BOARD_PLL_NSEL (1) /* Nsel = 1 */
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# define BOARD_FCLKOUT_FREQUENCY (204000000) /* 17 * 12,000,000 / 1 */
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# define BOARD_FCCO_FREQUENCY (204000000) /* Fclockout */
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#endif
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#define LPC43_CCLK BOARD_FCLKOUT_FREQUENCY
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#if defined(CONFIG_LPC43_BUS) || defined(CONFIG_LPC43_MCPWM) || defined(CONFIG_LPC43_I2C0) || defined(CONFIG_LPC43_I2S0) || defined(CONFIG_LPC43_I2S1) || defined(CONFIG_LPC43_CAN1)
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2016-01-15 19:17:30 +01:00
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# define BOARD_ABP1_CLKSRC BASE_APB_CLKSEL_XTAL
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# define BOARD_ABP1_FREQUENCY BOARD_XTAL_FREQUENCY
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2015-09-29 15:53:49 +02:00
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#endif
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#if defined(CONFIG_LPC43_BUS) || defined(CONFIG_LPC43_I2C1) || defined(CONFIG_LPC43_DAC) || defined(CONFIG_LPC43_ADC0) || defined(CONFIG_LPC43_ADC1) || defined(CONFIG_LPC43_CAN0)
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2016-01-15 19:17:30 +01:00
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# define BOARD_ABP3_CLKSRC BASE_APB_CLKSEL_XTAL
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# define BOARD_ABP3_FREQUENCY BOARD_XTAL_FREQUENCY
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2015-09-29 15:53:49 +02:00
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#endif
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2016-01-15 19:17:30 +01:00
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#define BOARD_IDIVA_DIVIDER (2)
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2015-09-29 15:53:49 +02:00
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#define BOARD_IDIVA_CLKSRC IDIVA_CLKSEL_PLL1
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2016-01-15 19:17:30 +01:00
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#define BOARD_IDIVA_FREQUENCY (BOARD_FCLKOUT_FREQUENCY/BOARD_IDIVA_DIVIDER)
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2015-09-29 15:53:49 +02:00
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2020-06-06 15:16:53 +02:00
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/* USB0 *********************************************************************/
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2019-08-14 14:34:18 +02:00
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2015-09-29 15:53:49 +02:00
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/* Settings needed in lpc43_cpu.c */
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2016-01-15 19:17:30 +01:00
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#define BOARD_USB0_CLKSRC PLL0USB_CLKSEL_XTAL
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2015-09-29 15:53:49 +02:00
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#define BOARD_USB0_MDIV 0x06167ffa /* Table 149 datsheet, valid for 12Mhz Fclkin */
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#define BOARD_USB0_NP_DIV 0x00302062 /* Table 149 datsheet, valid for 12Mhz Fclkin */
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2020-06-06 15:16:53 +02:00
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/* SPIFI clocking ***********************************************************/
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2019-08-14 14:34:18 +02:00
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2015-09-29 15:53:49 +02:00
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/* The SPIFI will receive clocking from a divider per the settings provided
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* in this file. The NuttX code will configure PLL1 as the input clock
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* for the selected divider
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*/
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#undef BOARD_SPIFI_PLL1 /* No division */
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#undef BOARD_SPIFI_DIVA /* Supports division by 1-4 */
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#undef BOARD_SPIFI_DIVB /* Supports division by 1-16 */
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#undef BOARD_SPIFI_DIVC /* Supports division by 1-16 */
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#undef BOARD_SPIFI_DIVD /* Supports division by 1-16 */
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#undef BOARD_SPIFI_DIVE /* Supports division by 1-256 */
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#if BOARD_FCLKOUT_FREQUENCY < 20000000
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# define BOARD_SPIFI_PLL1 1 /* Use PLL1 directly */
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#else
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# define BOARD_SPIFI_DIVB 1 /* Use IDIVB */
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#endif
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/* We need to configure the divider so that its output is as close to the
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* desired SCLK value. The peak data transfer rate will be about half of
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* this frequency in bytes per second.
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*/
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#if BOARD_FCLKOUT_FREQUENCY < 20000000
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# define BOARD_SPIFI_FREQUENCY BOARD_FCLKOUT_FREQUENCY /* 72Mhz? */
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#else
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# define BOARD_SPIFI_DIVIDER (14) /* 204MHz / 14 = 14.57MHz */
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# define BOARD_SPIFI_FREQUENCY (102000000) /* 204MHz / 14 = 14.57MHz */
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#endif
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2016-01-15 19:17:30 +01:00
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#if CONFIG_SPIFI_LIBRARY
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# define SPIFI_DEVICE_ALL 0 /**< Enables all devices in family */
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# define SPIFI_DEVICE_S25FL016K 0 /**< Enables Spansion S25FL016K device */
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# define SPIFI_DEVICE_S25FL032P 0 /**< Enables Spansion S25FL032P device */
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# define SPIFI_DEVICE_S25FL064P 0 /**< Enables Spansion S25FL064P device */
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# define SPIFI_DEVICE_S25FL129P_64K 0 /**< Enables Spansion S25FL129P (64K block) device */
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# define SPIFI_DEVICE_S25FL129P_256K 0 /**< Enables Spansion S25FL129P (256K block) device */
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# define SPIFI_DEVICE_S25FL164K 0 /**< Enables Spansion S25FL164K device */
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# define SPIFI_DEVICE_S25FL256S_64K 0 /**< Enables Spansion S25FL256S (64K block) device */
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# define SPIFI_DEVICE_S25FL256S_256K 0 /**< Enables Spansion S25FL256S (256K block) device */
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# define SPIFI_DEVICE_S25FL512S 0 /**< Enables Spansion S25FL512S device */
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# define SPIFI_DEVICE_MX25L1635E 0 /**< Enables Macronix MX25L1635E device */
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# define SPIFI_DEVICE_MX25L3235E 0 /**< Enables Macronix MX25L3235E device */
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# define SPIFI_DEVICE_MX25L8035E 0 /**< Enables Macronix MX25L8035E device */
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# define SPIFI_DEVICE_MX25L6435E 0 /**< Enables Macronix MX25L6435E device */
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# define SPIFI_DEVICE_W25Q32FV 0 /**< Enables Winbond W25Q32FV device */
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# define SPIFI_DEVICE_W25Q64FV 0 /**< Enables Winbond W25Q32V device */
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# define SPIFI_DEVICE_W25Q80BV 1 /**< Enables Winbond W25Q80BV device */
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# define SPIFI_DEVICE_REQUENCY_DIVIDER 2 /* PLL1 clock divider */
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#endif
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2020-06-06 15:16:53 +02:00
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/* UART clocking ************************************************************/
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2019-08-14 14:34:18 +02:00
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2015-09-29 15:53:49 +02:00
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/* Configure all U[S]ARTs to use the XTAL input frequency */
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#define BOARD_USART0_CLKSRC BASE_USART0_CLKSEL_XTAL
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#define BOARD_USART0_BASEFREQ BOARD_XTAL_FREQUENCY
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#define BOARD_UART1_CLKSRC BASE_UART1_CLKSEL_XTAL
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#define BOARD_UART1_BASEFREQ BOARD_XTAL_FREQUENCY
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#define BOARD_USART2_CLKSRC BASE_USART2_CLKSEL_XTAL
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#define BOARD_USART2_BASEFREQ BOARD_XTAL_FREQUENCY
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#define BOARD_USART3_CLKSRC BASE_USART3_CLKSEL_XTAL
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#define BOARD_USART3_BASEFREQ BOARD_XTAL_FREQUENCY
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2019-08-14 14:34:18 +02:00
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/* SSP clocking *************************************************************/
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2015-09-29 15:53:49 +02:00
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2019-08-14 14:34:18 +02:00
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/* BOARD_SSPX_BASEFREQ may be further divided by 2-254 to get the SSP clock.
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* If we want a usable range of 400KHz to 25MHz for the SSP, then:
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2015-09-29 15:53:49 +02:00
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*
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* 1. SSPCLK must be greater than (2*25MHz) = 50MHz, and
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* 2. SSPCLK must be less than (254*400Khz) = 101.6MHz.
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*
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*/
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2016-01-15 19:17:30 +01:00
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#define BOARD_SSP0_CLKSRC BASE_SSP0_CLKSEL_IDIVA
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#define BOARD_SSP0_BASEFREQ BOARD_IDIVA_FREQUENCY
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2015-09-29 15:53:49 +02:00
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2016-01-15 19:17:30 +01:00
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#define BOARD_SSP1_CLKSRC BASE_SSP1_CLKSEL_IDIVA
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#define BOARD_SSP1_BASEFREQ BOARD_IDIVA_FREQUENCY
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2015-09-29 15:53:49 +02:00
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2020-06-06 15:16:53 +02:00
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/* Clocking *****************************************************************/
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2019-08-14 14:34:18 +02:00
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2016-01-15 19:17:30 +01:00
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/* LED1 K2 GPIO0[8]
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2015-09-29 15:53:49 +02:00
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*
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2015-11-01 17:53:34 +01:00
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* LED index values for use with board_userled()
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2015-09-29 15:53:49 +02:00
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*/
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2016-01-15 19:17:30 +01:00
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#define BOARD_LED 0
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#define BOARD_NLEDS 1
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2015-09-29 15:53:49 +02:00
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2015-11-01 17:53:34 +01:00
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/* LED bits for use with board_userled_all() */
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2015-09-29 15:53:49 +02:00
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2016-01-15 19:17:30 +01:00
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#define BOARD_LED_BIT (1 << BOARD_LED)
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2015-09-29 15:53:49 +02:00
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/* If CONFIG_ARCH_LEDS is defined, the LEDs will be controlled as follows
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* for NuttX debug functionality (where NC means "No Change"). If
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* CONFIG_ARCH_LEDS is not defined, then the LEDs are completely under
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* control of the application. The following interfaces are then available
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* for application control of the LEDs:
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*
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2020-06-05 12:08:02 +02:00
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* uint32_t board_userled_initialize(void);
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2015-11-01 17:53:34 +01:00
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* void board_userled(int led, bool ledon);
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2020-06-06 12:35:44 +02:00
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* void board_userled_all(uint32_t ledset);
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2015-09-29 15:53:49 +02:00
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*/
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2020-06-06 15:16:53 +02:00
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2016-01-15 19:17:30 +01:00
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/* LED */
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#define LED_STARTED 0 /* OFF */
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#define LED_HEAPALLOCATE 0 /* OFF */
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#define LED_IRQSENABLED 0 /* OFF */
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#define LED_STACKCREATED 1 /* ON */
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#define LED_INIRQ 2 /* NC */
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#define LED_SIGNAL 2 /* NC */
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#define LED_ASSERTION 2 /* NC */
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#define LED_PANIC 3 /* Flashing */
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2015-09-29 15:53:49 +02:00
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/* UART Pins ****************************************************************/
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2019-08-14 14:34:18 +02:00
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/* The following definitions must be provided so that the LPC43 serial
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2015-09-29 15:53:49 +02:00
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* driver can set up the U[S]ART for the serial console properly (see the
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* file arch/arc/src/lpc43xx/lpc43*_pinconf.h for more info).
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*/
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2016-01-15 19:17:30 +01:00
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#define PINCONF_U0_TXD PINCONF_U0_TXD_3
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#define PINCONF_U0_RXD PINCONF_U0_RXD_3
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#define PINCONF_U0_DIR PINCONF_U0_DIR_3
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#define PINCONF_U1_TXD PINCONF_U1_TXD_1
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#define PINCONF_U1_RXD PINCONF_U1_RXD_1
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2015-09-29 15:53:49 +02:00
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2016-01-15 19:17:30 +01:00
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#define PINCONF_U2_TXD PINCONF_U2_TXD_2
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#define PINCONF_U2_RXD PINCONF_U2_RXD_2
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#define PINCONF_U2_DIR PINCONF_U2_DIR_2
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2015-09-29 15:53:49 +02:00
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2016-01-15 19:17:30 +01:00
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#define PINCONF_U3_TXD PINCONF_U3_TXD_2
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#define PINCONF_U3_RXD PINCONF_U3_RXD_2
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#define PINCONF_U3_DIR PINCONF_U3_DIR_2
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2015-09-29 15:53:49 +02:00
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2016-01-15 19:17:30 +01:00
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/* I2C1 pins, not really accessible on the board */
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2015-09-29 15:53:49 +02:00
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2016-01-15 19:17:30 +01:00
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#define PINCONF_I2C1_SCL PINCONF_I2C1_SCL_1
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#define PINCONF_I2C1_SDA PINCONF_I2C1_SDA_1
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2015-09-29 15:53:49 +02:00
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2016-01-15 19:17:30 +01:00
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/* SSP1 pins */
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2015-09-29 15:53:49 +02:00
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2016-01-15 19:17:30 +01:00
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#define PINCONF_SSP1_MISO PINCONF_SSP1_MISO_3
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#define PINCONF_SSP1_MOSI PINCONF_SSP1_MOSI_3
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#define PINCONF_SSP1_SCK PINCONF_SSP1_SCK_1
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#define PINCONF_SSP1_SSEL PINCONF_SSP1_SSEL_1
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2015-09-29 15:53:49 +02:00
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2022-01-15 03:44:35 +01:00
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#endif /* __BOARDS_ARM_LPC43XX_LPC4370_LINK2_INCLUDE_BOARD_H */
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