2014-10-19 02:40:08 +02:00
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/************************************************************************************
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* arch/arm/src/efm32/efm32_gpioirq.c
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*
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2015-09-05 15:50:02 +02:00
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* Copyright (C) 2014-2015 Gregory Nutt. All rights reserved.
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2014-10-19 02:40:08 +02:00
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <stdbool.h>
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2014-10-20 15:09:15 +02:00
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#include <assert.h>
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2014-10-19 02:40:08 +02:00
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2014-10-20 15:09:15 +02:00
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#include <nuttx/arch.h>
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2016-02-14 02:11:09 +01:00
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#include <nuttx/irq.h>
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2014-10-20 15:09:15 +02:00
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#include "up_arch.h"
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2019-05-25 02:51:49 +02:00
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#include "hardware/efm32_gpio.h"
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2014-10-19 02:40:08 +02:00
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#include "efm32_gpio.h"
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2015-09-05 10:40:34 +02:00
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#include "efm32_bitband.h"
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2014-10-19 02:40:08 +02:00
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#ifdef CONFIG_EFM32_GPIO_IRQ
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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2014-10-20 15:09:15 +02:00
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/************************************************************************************
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* Private Functions
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************************************************************************************/
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/************************************************************************************
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* Name: efm32_getport
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*
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* Description:
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* Extract the encoded port number
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*
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************************************************************************************/
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static inline uint8_t efm32_getport(gpio_pinset_t cfgset)
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{
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return (uint8_t)((cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT);
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}
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/************************************************************************************
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* Name: efm32_getpin
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*
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* Description:
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* Extract the encoded pin number
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*
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2014-10-19 02:40:08 +02:00
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************************************************************************************/
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2014-10-20 15:09:15 +02:00
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static inline uint8_t efm32_getpin(gpio_pinset_t cfgset)
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{
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return (uint8_t)((cfgset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT);
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}
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/************************************************************************************
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* Name: efm32_gpio_interrupt
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*
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* Description:
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* Common GPIO interrupt handling logic
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*
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************************************************************************************/
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static int efm32_gpio_interrupt(uint32_t mask, void *context)
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{
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uint32_t pending;
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uint32_t bit;
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int irq;
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/* Get the set of even/odd, pending, enabled interrupts */
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pending = getreg32(EFM32_GPIO_IF) & getreg32(EFM32_GPIO_IEN) & mask;
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putreg32(pending, EFM32_GPIO_IFC);
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/* Then dispatch each interrupt */
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for (bit = 1, irq = EFM32_IRQ_EXTI0; pending != 0; bit <<= 1, irq++)
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{
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if ((pending & bit) != 0)
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{
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/* Re-deliver the IRQ (recurses! We got here from irq_dispatch!) */
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irq_dispatch(irq, context);
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/* Remove this from the set of pending interrupts */
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pending &= ~bit;
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}
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}
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return OK;
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}
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/************************************************************************************
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* Name: efm32_even_interrupt
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*
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* Description:
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* Even GPIO interrupt handling logic
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*
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************************************************************************************/
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2017-02-27 13:27:56 +01:00
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static int efm32_even_interrupt(int irq, void *context, FAR void *arg)
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2014-10-20 15:09:15 +02:00
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{
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return efm32_gpio_interrupt(0x00005555, context);
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}
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/************************************************************************************
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* Name: efm32_even_interrupt
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*
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* Description:
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* Even GPIO interrupt handling logic
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*
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************************************************************************************/
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2017-02-27 13:27:56 +01:00
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static int efm32_odd_interrupt(int irq, void *context, FAR void *arg)
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2014-10-20 15:09:15 +02:00
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{
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return efm32_gpio_interrupt(0x0000aaaa, context);
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}
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2014-10-19 02:40:08 +02:00
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/************************************************************************************
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2020-01-14 00:37:54 +01:00
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* Public Functions
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2014-10-19 02:40:08 +02:00
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************************************************************************************/
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/************************************************************************************
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* Name: efm32_gpioirqinitialize
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*
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* Description:
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* Initialize logic to support a second level of interrupt decoding for PIO pins.
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*
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************************************************************************************/
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void efm32_gpioirqinitialize(void)
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{
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2014-10-20 15:09:15 +02:00
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/* Initialize GPIO interrupt registers, disabling GPIO interrupts at the source */
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putreg32(0, EFM32_GPIO_EXTIRISE);
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putreg32(0, EFM32_GPIO_EXTIFALL);
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putreg32(0, EFM32_GPIO_IEN);
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/* Attach the even and odd interrupt handlers */
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2017-02-27 13:27:56 +01:00
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DEBUGVERIFY(irq_attach(EFM32_IRQ_GPIO_EVEN, efm32_even_interrupt, NULL));
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DEBUGVERIFY(irq_attach(EFM32_IRQ_GPIO_ODD, efm32_odd_interrupt, NULL));
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2014-10-20 15:09:15 +02:00
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/* Enable GPIO even and odd interrupts at the NVIC */
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up_enable_irq(EFM32_IRQ_GPIO_ODD);
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up_enable_irq(EFM32_IRQ_GPIO_EVEN);
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2014-10-19 02:40:08 +02:00
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}
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/************************************************************************************
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* Name: efm32_gpioirq
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*
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* Description:
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* Configure an interrupt for the specified PIO pin.
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*
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************************************************************************************/
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void efm32_gpioirq(gpio_pinset_t pinset)
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{
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2014-10-20 15:09:15 +02:00
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irqstate_t flags;
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unsigned int shift;
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uintptr_t regaddr;
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uint32_t regval;
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uint32_t bit;
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uint8_t port;
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uint8_t pin;
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/* Get basic pin configuration information */
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2014-10-24 02:16:57 +02:00
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port = efm32_getport(pinset);
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pin = efm32_getpin(pinset);
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2014-10-20 15:09:15 +02:00
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bit = ((uint32_t)1 << pin);
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/* Make sure that the pin interrupt is disabled */
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2016-02-14 02:11:09 +01:00
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flags = enter_critical_section();
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2014-10-20 15:09:15 +02:00
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regval = getreg32(EFM32_GPIO_IEN);
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regval &= ~bit;
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putreg32(regval, EFM32_GPIO_IEN);
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/* Set the interrupt port */
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if (pin < 8)
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{
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regaddr = EFM32_GPIO_EXTIPSELL;
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shift = (unsigned int)pin << 2;
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}
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else
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{
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regaddr = EFM32_GPIO_EXTIPSELH;
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shift = (unsigned int)(pin - 8) << 2;
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}
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regval = getreg32(regaddr);
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regval &= ~(7 << shift);
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regval |= ((uint32_t)port << shift);
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putreg32(regval, regaddr);
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/* Set/clear rising edge interrupt detection */
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regval = getreg32(EFM32_GPIO_EXTIRISE);
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if ((pinset & GPIO_INT_RISING) != 0)
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{
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regval |= bit;
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}
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else
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{
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regval &= ~bit;
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}
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putreg32(regval, EFM32_GPIO_EXTIRISE);
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/* Set/clear rising edge interrupt detection */
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regval = getreg32(EFM32_GPIO_EXTIFALL);
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if ((pinset & GPIO_INT_FALLING) != 0)
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{
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regval |= bit;
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}
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else
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{
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regval &= ~bit;
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}
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putreg32(regval, EFM32_GPIO_EXTIFALL);
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2016-02-14 02:11:09 +01:00
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leave_critical_section(flags);
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2014-10-19 02:40:08 +02:00
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}
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/************************************************************************************
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* Name: efm32_gpioirqenable
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*
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* Description:
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* Enable the interrupt for specified PIO IRQ
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*
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************************************************************************************/
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void efm32_gpioirqenable(int irq)
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{
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2014-10-20 15:09:15 +02:00
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if (irq >= EFM32_IRQ_EXTI0 && irq <= EFM32_IRQ_EXTI15)
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{
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/* Enable the interrupt associated with the pin */
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2015-09-05 15:50:02 +02:00
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#ifndef CONFIG_EFM32_BITBAND
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2015-09-05 10:40:34 +02:00
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irqstate_t flags;
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uint32_t regval;
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uint32_t bit;
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2014-10-20 15:09:15 +02:00
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bit = ((uint32_t)1 << (irq - EFM32_IRQ_EXTI0));
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2016-02-14 02:11:09 +01:00
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flags = enter_critical_section();
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2014-10-20 15:09:15 +02:00
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regval = getreg32(EFM32_GPIO_IEN);
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regval |= bit;
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putreg32(regval, EFM32_GPIO_IEN);
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2016-02-14 02:11:09 +01:00
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leave_critical_section(flags);
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2015-09-05 10:40:34 +02:00
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#else
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2015-10-07 19:39:06 +02:00
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bitband_set_peripheral(EFM32_GPIO_IEN, (irq - EFM32_IRQ_EXTI0), 1);
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2015-09-05 10:40:34 +02:00
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#endif
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2014-10-20 15:09:15 +02:00
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}
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2014-10-19 02:40:08 +02:00
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}
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/************************************************************************************
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* Name: efm32_gpioirqdisable
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*
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* Description:
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* Disable the interrupt for specified PIO IRQ
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*
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************************************************************************************/
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void efm32_gpioirqdisable(int irq)
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{
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2014-10-20 15:09:15 +02:00
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if (irq >= EFM32_IRQ_EXTI0 && irq <= EFM32_IRQ_EXTI15)
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{
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/* Enable the interrupt associated with the pin */
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2015-09-05 15:50:02 +02:00
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#ifndef CONFIG_EFM32_BITBAND
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2015-09-05 10:40:34 +02:00
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irqstate_t flags;
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uint32_t regval;
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uint32_t bit;
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2015-09-05 15:50:02 +02:00
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2014-10-20 15:09:15 +02:00
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bit = ((uint32_t)1 << (irq - EFM32_IRQ_EXTI0));
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2016-02-14 02:11:09 +01:00
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flags = enter_critical_section();
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2014-10-20 15:09:15 +02:00
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regval = getreg32(EFM32_GPIO_IEN);
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regval &= ~bit;
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putreg32(regval, EFM32_GPIO_IEN);
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2016-02-14 02:11:09 +01:00
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leave_critical_section(flags);
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2015-09-05 10:40:34 +02:00
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#else
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2015-10-07 19:39:06 +02:00
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bitband_set_peripheral(EFM32_GPIO_IEN, (irq - EFM32_IRQ_EXTI0), 0);
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2015-09-05 10:40:34 +02:00
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#endif
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2014-10-20 15:09:15 +02:00
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}
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2014-10-19 02:40:08 +02:00
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}
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2015-09-05 10:20:24 +02:00
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/************************************************************************************
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* Name: efm32_gpioirqclear
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*
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* Description:
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* Disable the interrupt for specified PIO IRQ
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*
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************************************************************************************/
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void efm32_gpioirqclear(int irq)
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{
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if (irq >= EFM32_IRQ_EXTI0 && irq <= EFM32_IRQ_EXTI15)
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{
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/* Enable the interrupt associated with the pin */
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2015-09-05 15:50:02 +02:00
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#ifndef CONFIG_EFM32_BITBAND
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2015-09-05 10:40:34 +02:00
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irqstate_t flags;
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uint32_t regval;
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uint32_t bit;
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2015-09-05 10:20:24 +02:00
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bit = ((uint32_t)1 << (irq - EFM32_IRQ_EXTI0));
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2016-02-14 02:11:09 +01:00
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flags = enter_critical_section();
|
2015-09-05 10:20:24 +02:00
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regval = getreg32(EFM32_GPIO_IFC);
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regval |= bit;
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putreg32(regval, EFM32_GPIO_IFC);
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2016-02-14 02:11:09 +01:00
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leave_critical_section(flags);
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2015-09-05 10:40:34 +02:00
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|
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#else
|
2015-10-07 19:39:06 +02:00
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|
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bitband_set_peripheral(EFM32_GPIO_IFC, (irq - EFM32_IRQ_EXTI0), 1);
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2015-09-05 10:40:34 +02:00
|
|
|
#endif
|
2015-09-05 10:20:24 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-10-19 02:40:08 +02:00
|
|
|
#endif /* CONFIG_EFM32_GPIO_IRQ */
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