nuttx/arch/x86_64/include/irq.h

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Flat address x86_64 port of Nuttx (#411) * arch: x86_64: Pour-in the x86_64 code from cRTOS repository, excluding modifications of NuttX kernel, jailhouse support and linux compatibility layer * arch: x86_64: Refactor x86_64 loading procedure for better comprehension and included support for multiboot2 * arch: x86_64: Locate the kernel at 4GB~ and modify the page table initializing procedure accordingly * arch: x86_64: Implemented kconfig option for various x86_64 capabilities, dynamic probe and check capability on lowsetup before enabling * arch: x86_64: inte64_check_capability: Use Marco to prettify the capability checking procedure * arch: x86_64: intel64_timerisr.c: Refactor with new frequency calibrating method * arch: x86_64: Fix C alias of page table and GDT/IST * arch: x86_64: Reload GTDR with GDT in high address in up_lowsetup * arch: x86_64: Consolidate MSR definition in arch/arch.h * arch: x86_64: Edit the way of handling GDT/IST in C into structures * arch: x86_64: Correct the starting point of isr/irq stack * arch: x86_64: Update up_initialize.c with the new initializing procedure * arch: x86_64: up_map_region now take flags instead of assuming WR/PRESENT * arch: x86_64: Overhual of interrupt initialization procedure * arch: x86_64: Properly configure the heap to be memory as [_ebss, end of memory] * arch: x86_64: Try to probe the TSC frequency, fall-back to user specified frequency on failure * arch: x86_64: Remove debug printing during restore_aux, causing infinite CTX bug * arch: x86_64: for X86 16500 serial interrupt to work, OUT2 of MCR must be 1. Make it stuck at 1 after boot * arch: x86_64: Correctly apply license header, comment and format code * arch: x86_64: properly send a SIGFPE on floating point error * arch: x86_64: Remove unused variable in up_restore_auxstate * arch: x86_64: properly trash the processor with an infinite loop * arch: x86_64: Fix typo in ISR handler causing ISR not handled * arch: x86_64: Fix possibile race conditions with scheduler debug option on in signal handling path * arch: x86_64: Fix typo in MSR_X2APIC_LVTT_TSC_DEADLINE * arch: x86_64: Migrate tickless implementation to the new MSR naming and frequency calibration method * board: x86_64: qemu: Add guard to exclude up_netinitialize when compiling without net support * arch: x86_64: update defconfigs * arch: x86_64: rename qemu as qemu-intel64 * arch: x86_64: update Board readme
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/****************************************************************************
* arch/x86_64/include/irq.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* This file should never be included directly but, rather, only indirectly
Flat address x86_64 port of Nuttx (#411) * arch: x86_64: Pour-in the x86_64 code from cRTOS repository, excluding modifications of NuttX kernel, jailhouse support and linux compatibility layer * arch: x86_64: Refactor x86_64 loading procedure for better comprehension and included support for multiboot2 * arch: x86_64: Locate the kernel at 4GB~ and modify the page table initializing procedure accordingly * arch: x86_64: Implemented kconfig option for various x86_64 capabilities, dynamic probe and check capability on lowsetup before enabling * arch: x86_64: inte64_check_capability: Use Marco to prettify the capability checking procedure * arch: x86_64: intel64_timerisr.c: Refactor with new frequency calibrating method * arch: x86_64: Fix C alias of page table and GDT/IST * arch: x86_64: Reload GTDR with GDT in high address in up_lowsetup * arch: x86_64: Consolidate MSR definition in arch/arch.h * arch: x86_64: Edit the way of handling GDT/IST in C into structures * arch: x86_64: Correct the starting point of isr/irq stack * arch: x86_64: Update up_initialize.c with the new initializing procedure * arch: x86_64: up_map_region now take flags instead of assuming WR/PRESENT * arch: x86_64: Overhual of interrupt initialization procedure * arch: x86_64: Properly configure the heap to be memory as [_ebss, end of memory] * arch: x86_64: Try to probe the TSC frequency, fall-back to user specified frequency on failure * arch: x86_64: Remove debug printing during restore_aux, causing infinite CTX bug * arch: x86_64: for X86 16500 serial interrupt to work, OUT2 of MCR must be 1. Make it stuck at 1 after boot * arch: x86_64: Correctly apply license header, comment and format code * arch: x86_64: properly send a SIGFPE on floating point error * arch: x86_64: Remove unused variable in up_restore_auxstate * arch: x86_64: properly trash the processor with an infinite loop * arch: x86_64: Fix typo in ISR handler causing ISR not handled * arch: x86_64: Fix possibile race conditions with scheduler debug option on in signal handling path * arch: x86_64: Fix typo in MSR_X2APIC_LVTT_TSC_DEADLINE * arch: x86_64: Migrate tickless implementation to the new MSR naming and frequency calibration method * board: x86_64: qemu: Add guard to exclude up_netinitialize when compiling without net support * arch: x86_64: update defconfigs * arch: x86_64: rename qemu as qemu-intel64 * arch: x86_64: update Board readme
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* through nuttx/irq.h
*/
#ifndef __ARCH_X86_64_INCLUDE_IRQ_H
#define __ARCH_X86_64_INCLUDE_IRQ_H
/****************************************************************************
* Included Files
****************************************************************************/
/* Include NuttX-specific IRQ definitions */
#include <nuttx/irq.h>
/* Include chip-specific IRQ definitions (including IRQ numbers) */
#include <arch/chip/irq.h>
/* Include architecture-specific IRQ definitions (including register save
* structure and up_irq_save()/up_irq_restore() macros).
*/
#ifdef CONFIG_ARCH_INTEL64
# include <arch/intel64/irq.h>
Flat address x86_64 port of Nuttx (#411) * arch: x86_64: Pour-in the x86_64 code from cRTOS repository, excluding modifications of NuttX kernel, jailhouse support and linux compatibility layer * arch: x86_64: Refactor x86_64 loading procedure for better comprehension and included support for multiboot2 * arch: x86_64: Locate the kernel at 4GB~ and modify the page table initializing procedure accordingly * arch: x86_64: Implemented kconfig option for various x86_64 capabilities, dynamic probe and check capability on lowsetup before enabling * arch: x86_64: inte64_check_capability: Use Marco to prettify the capability checking procedure * arch: x86_64: intel64_timerisr.c: Refactor with new frequency calibrating method * arch: x86_64: Fix C alias of page table and GDT/IST * arch: x86_64: Reload GTDR with GDT in high address in up_lowsetup * arch: x86_64: Consolidate MSR definition in arch/arch.h * arch: x86_64: Edit the way of handling GDT/IST in C into structures * arch: x86_64: Correct the starting point of isr/irq stack * arch: x86_64: Update up_initialize.c with the new initializing procedure * arch: x86_64: up_map_region now take flags instead of assuming WR/PRESENT * arch: x86_64: Overhual of interrupt initialization procedure * arch: x86_64: Properly configure the heap to be memory as [_ebss, end of memory] * arch: x86_64: Try to probe the TSC frequency, fall-back to user specified frequency on failure * arch: x86_64: Remove debug printing during restore_aux, causing infinite CTX bug * arch: x86_64: for X86 16500 serial interrupt to work, OUT2 of MCR must be 1. Make it stuck at 1 after boot * arch: x86_64: Correctly apply license header, comment and format code * arch: x86_64: properly send a SIGFPE on floating point error * arch: x86_64: Remove unused variable in up_restore_auxstate * arch: x86_64: properly trash the processor with an infinite loop * arch: x86_64: Fix typo in ISR handler causing ISR not handled * arch: x86_64: Fix possibile race conditions with scheduler debug option on in signal handling path * arch: x86_64: Fix typo in MSR_X2APIC_LVTT_TSC_DEADLINE * arch: x86_64: Migrate tickless implementation to the new MSR naming and frequency calibration method * board: x86_64: qemu: Add guard to exclude up_netinitialize when compiling without net support * arch: x86_64: update defconfigs * arch: x86_64: rename qemu as qemu-intel64 * arch: x86_64: update Board readme
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#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
/* This holds a references to the current interrupt level register storage
* structure. If is non-NULL only during interrupt processing.
*/
extern volatile uint64_t *g_current_regs;
#endif
Flat address x86_64 port of Nuttx (#411) * arch: x86_64: Pour-in the x86_64 code from cRTOS repository, excluding modifications of NuttX kernel, jailhouse support and linux compatibility layer * arch: x86_64: Refactor x86_64 loading procedure for better comprehension and included support for multiboot2 * arch: x86_64: Locate the kernel at 4GB~ and modify the page table initializing procedure accordingly * arch: x86_64: Implemented kconfig option for various x86_64 capabilities, dynamic probe and check capability on lowsetup before enabling * arch: x86_64: inte64_check_capability: Use Marco to prettify the capability checking procedure * arch: x86_64: intel64_timerisr.c: Refactor with new frequency calibrating method * arch: x86_64: Fix C alias of page table and GDT/IST * arch: x86_64: Reload GTDR with GDT in high address in up_lowsetup * arch: x86_64: Consolidate MSR definition in arch/arch.h * arch: x86_64: Edit the way of handling GDT/IST in C into structures * arch: x86_64: Correct the starting point of isr/irq stack * arch: x86_64: Update up_initialize.c with the new initializing procedure * arch: x86_64: up_map_region now take flags instead of assuming WR/PRESENT * arch: x86_64: Overhual of interrupt initialization procedure * arch: x86_64: Properly configure the heap to be memory as [_ebss, end of memory] * arch: x86_64: Try to probe the TSC frequency, fall-back to user specified frequency on failure * arch: x86_64: Remove debug printing during restore_aux, causing infinite CTX bug * arch: x86_64: for X86 16500 serial interrupt to work, OUT2 of MCR must be 1. Make it stuck at 1 after boot * arch: x86_64: Correctly apply license header, comment and format code * arch: x86_64: properly send a SIGFPE on floating point error * arch: x86_64: Remove unused variable in up_restore_auxstate * arch: x86_64: properly trash the processor with an infinite loop * arch: x86_64: Fix typo in ISR handler causing ISR not handled * arch: x86_64: Fix possibile race conditions with scheduler debug option on in signal handling path * arch: x86_64: Fix typo in MSR_X2APIC_LVTT_TSC_DEADLINE * arch: x86_64: Migrate tickless implementation to the new MSR naming and frequency calibration method * board: x86_64: qemu: Add guard to exclude up_netinitialize when compiling without net support * arch: x86_64: update defconfigs * arch: x86_64: rename qemu as qemu-intel64 * arch: x86_64: update Board readme
2020-03-04 00:29:13 +01:00
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Name: up_cpu_index
*
* Description:
* Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
* corresponds to the currently executing CPU.
*
* Input Parameters:
* None
*
* Returned Value:
* An integer index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
* corresponds to the currently executing CPU.
*
****************************************************************************/
#define up_cpu_index() (0)
/****************************************************************************
* Inline functions
****************************************************************************/
/****************************************************************************
* Name: up_interrupt_context
*
* Description:
* Return true is we are currently executing in the interrupt handler
* context.
*
****************************************************************************/
#define up_interrupt_context() (g_current_regs != NULL)
Flat address x86_64 port of Nuttx (#411) * arch: x86_64: Pour-in the x86_64 code from cRTOS repository, excluding modifications of NuttX kernel, jailhouse support and linux compatibility layer * arch: x86_64: Refactor x86_64 loading procedure for better comprehension and included support for multiboot2 * arch: x86_64: Locate the kernel at 4GB~ and modify the page table initializing procedure accordingly * arch: x86_64: Implemented kconfig option for various x86_64 capabilities, dynamic probe and check capability on lowsetup before enabling * arch: x86_64: inte64_check_capability: Use Marco to prettify the capability checking procedure * arch: x86_64: intel64_timerisr.c: Refactor with new frequency calibrating method * arch: x86_64: Fix C alias of page table and GDT/IST * arch: x86_64: Reload GTDR with GDT in high address in up_lowsetup * arch: x86_64: Consolidate MSR definition in arch/arch.h * arch: x86_64: Edit the way of handling GDT/IST in C into structures * arch: x86_64: Correct the starting point of isr/irq stack * arch: x86_64: Update up_initialize.c with the new initializing procedure * arch: x86_64: up_map_region now take flags instead of assuming WR/PRESENT * arch: x86_64: Overhual of interrupt initialization procedure * arch: x86_64: Properly configure the heap to be memory as [_ebss, end of memory] * arch: x86_64: Try to probe the TSC frequency, fall-back to user specified frequency on failure * arch: x86_64: Remove debug printing during restore_aux, causing infinite CTX bug * arch: x86_64: for X86 16500 serial interrupt to work, OUT2 of MCR must be 1. Make it stuck at 1 after boot * arch: x86_64: Correctly apply license header, comment and format code * arch: x86_64: properly send a SIGFPE on floating point error * arch: x86_64: Remove unused variable in up_restore_auxstate * arch: x86_64: properly trash the processor with an infinite loop * arch: x86_64: Fix typo in ISR handler causing ISR not handled * arch: x86_64: Fix possibile race conditions with scheduler debug option on in signal handling path * arch: x86_64: Fix typo in MSR_X2APIC_LVTT_TSC_DEADLINE * arch: x86_64: Migrate tickless implementation to the new MSR naming and frequency calibration method * board: x86_64: qemu: Add guard to exclude up_netinitialize when compiling without net support * arch: x86_64: update defconfigs * arch: x86_64: rename qemu as qemu-intel64 * arch: x86_64: update Board readme
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#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_X86_64_INCLUDE_IRQ_H */