196 lines
7.1 KiB
C
196 lines
7.1 KiB
C
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/****************************************************************************
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* boards/arm/sama5/giant-board/include/board.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __BOARDS_ARM_SAMA5_GIANT_BOARD_INCLUDE_BOARD_H
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#define __BOARDS_ARM_SAMA5_GIANT_BOARD_INCLUDE_BOARD_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#ifndef __ASSEMBLY__
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# include <stdbool.h>
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# include <nuttx/irq.h>
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#endif
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Clocking *****************************************************************/
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/* After power-on reset, the SAMA5 device is running on a 12MHz internal RC.
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* These definitions will configure operational clocking.
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*/
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/* On-board crystal frequencies */
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#define BOARD_MAINOSC_FREQUENCY (24000000) /* MAINOSC: 12MHz crystal on-board */
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#define BOARD_SLOWCLK_FREQUENCY (32768) /* Slow Clock: 32.768KHz */
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#if defined(CONFIG_SAMA5_BOOT_SDRAM)
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/* When booting from SDRAM, NuttX is loaded in SDRAM by an intermediate
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* bootloader.
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* That bootloader had to have already configured the PLL and SDRAM for
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* proper operation.
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*
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* In this case, we do not reconfigure the clocking.
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* Rather, we need to query the register settings to determine the clock
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* frequencies.
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* We can only assume that the Main clock source is the on-board 24MHz
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* crystal.
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*/
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# include <arch/board/board_sdram.h>
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#elif defined(CONFIG_GIANT_BOARD_492MHZ)
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/* This configuration results in a CPU clock of 492MHz.
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*
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* In this configuration, UPLL is the source of the UHPHS clock (if enabled).
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*/
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# include <arch/board/board_492mhz.h>
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#endif
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/* LED definitions **********************************************************/
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/* There is a status LED on board the Giant Board.
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*
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* ------------------------------ ------------------- ---------------------
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* SAMA5D27 PIO SIGNAL USAGE
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* ------------------------------ ------------------- ---------------------
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* PA6 STATUS_LED Orange LED
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* ------------------------------ ------------------- ---------------------
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*/
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/* LED index values for use with board_userled() */
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#define BOARD_ORANGE 0
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#define BOARD_NLEDS 1
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/* LED bits for use with board_userled_all() */
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#define BOARD_ORANGE_BIT (1 << BOARD_ORANGE)
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/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is
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* defined. In that case, the usage by the board port is defined in
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* include/board.h and src/sam_leds.c. The LEDs are used to encode OS-related
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* events as follows. Note that only the GREEN LED is used in this case
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*
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* SYMBOL Val Meaning Green LED
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* ----------------- --- ----------------------- -----------
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*/
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#define LED_STARTED 0 /* NuttX has been started OFF */
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#define LED_HEAPALLOCATE 0 /* Heap has been allocated OFF */
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#define LED_IRQSENABLED 0 /* Interrupts enabled OFF */
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#define LED_STACKCREATED 1 /* Idle stack created ON */
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#define LED_INIRQ 2 /* In an interrupt N/C */
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#define LED_SIGNAL 2 /* In a signal handler N/C */
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#define LED_ASSERTION 2 /* An assertion failed N/C */
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#define LED_PANIC 3 /* The system has crashed Flash */
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#undef LED_IDLE /* MCU is is sleep mode Not used */
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/* Thus if the Orange LED is statically on, NuttX has successfully booted
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* and is, apparently, running normally.
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* If LED is flashing at approximately 2Hz, then a fatal error has been
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* detected and the system has halted.
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*/
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/* Pin disambiguation *******************************************************/
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/* Alternative pin selections are provided with a numeric suffix like _1, _2,
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* etc. Drivers, however, will use the pin selection without the numeric
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* suffix.
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* Additional definitions are required in this board.h file.
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* For example, if we wanted the PCK0on PB26, then the following definition
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* should appear in the board.h header file for that board:
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*
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* #define PIO_PMC_PCK0 PIO_PMC_PCK0_1
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*
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* The PCK logic will then automatically configure PB26 as the PCK0 pin.
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*/
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/* UART1. There is a TTL serial connection available on
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* pins RX and TX. This is be driven by UART1.
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*
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* ---- ------------------------ -------------
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* J1/2 SCHEMATIC SAMA5D2
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* PIN NAME(s) PIO FUNCTION
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* ---- ------------------------ -------------
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* 14 UART1_RX PD3 UTXD1
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* 15 UART1_TX PD2 URXD1
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* ---- ------------------------ -------------
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*/
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#define PIO_UART1_RXD PIO_UART1_RXD_1
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#define PIO_UART1_TXD PIO_UART1_TXD_1
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/* FLEXCOM4 is available as a UART.
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*
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* ----- ------- -------------
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* J1/2 BOARD SAMA5D2
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* PIN NAME PIO FUNCTION
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* ----- ------- -------------
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* 6 AD2 PD21 FLEXCOM4
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* 9 AD3 PD22 FLEXCOM4
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* ----- ------- -------------
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*/
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#define PIO_FLEXCOM4_IO0 PIO_FLEXCOM4_IO0_2
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#define PIO_FLEXCOM4_IO1 PIO_FLEXCOM4_IO1_2
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/* PIO pins */
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#define PIO_TX IO_
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/* SDIO - Used for both Port 0 & 1 ******************************************/
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/* 386 KHz for initial inquiry stuff */
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#define BOARD_SDMMC_IDMODE_PRESCALER SDMMC_SYSCTL_SDCLKFS_DIV256
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#define BOARD_SDMMC_IDMODE_DIVISOR SDMMC_SYSCTL_DVS_DIV(2)
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/* 24.8MHz for other modes */
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#define BOARD_SDMMC_MMCMODE_PRESCALER SDMMC_SYSCTL_SDCLKFS_DIV8
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#define BOARD_SDMMC_MMCMODE_DIVISOR SDMMC_SYSCTL_DVS_DIV(1)
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#define BOARD_SDMMC_SD1MODE_PRESCALER SDMMC_SYSCTL_SDCLKFS_DIV8
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#define BOARD_SDMMC_SD1MODE_DIVISOR SDMMC_SYSCTL_DVS_DIV(1)
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#define BOARD_SDMMC_SD4MODE_PRESCALER SDMMC_SYSCTL_SDCLKFS_DIV8
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#define BOARD_SDMMC_SD4MODE_DIVISOR SDMMC_SYSCTL_DVS_DIV(1)
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/****************************************************************************
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* Assembly Language Macros
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****************************************************************************/
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#ifdef __ASSEMBLY__
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.macro config_sdram
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.endm
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#endif /* __ASSEMBLY__ */
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#endif /* __BOARDS_ARM_SAMA5_GIANT_BOARD_INCLUDE_BOARD_H */
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