2016-10-12 21:11:05 +02:00
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/****************************************************************************
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* arch/xtensa/include/syscall.h
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*
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2021-03-28 17:44:37 +02:00
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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2016-10-12 21:11:05 +02:00
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*
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2021-03-28 17:44:37 +02:00
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* http://www.apache.org/licenses/LICENSE-2.0
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2016-10-12 21:11:05 +02:00
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*
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2021-03-28 17:44:37 +02:00
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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2016-10-12 21:11:05 +02:00
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*
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****************************************************************************/
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2020-04-05 23:00:04 +02:00
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/* This file should never be included directly but, rather, only indirectly
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2016-10-12 21:11:05 +02:00
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* through include/syscall.h or include/sys/sycall.h
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*/
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#ifndef __ARCH_XTENSA_INCLUDE_SYSCALL_H
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#define __ARCH_XTENSA_INCLUDE_SYSCALL_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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2022-02-15 07:27:26 +01:00
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#include <nuttx/config.h>
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2022-03-24 22:12:55 +01:00
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2022-02-15 07:27:26 +01:00
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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#endif
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#ifdef CONFIG_LIB_SYSCALL
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# include <syscall.h>
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#endif
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2022-03-24 22:12:55 +01:00
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#include <arch/xtensa/core.h>
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#include <arch/xtensa/xtensa_corebits.h>
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2022-01-11 08:08:42 +01:00
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2016-10-12 21:11:05 +02:00
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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2022-03-24 22:12:55 +01:00
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/* Select software interrupt number for context-switch.
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* The SW interrupt level must be greater than XCHAL_SYSCALL_LEVEL
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* and less than XCHAL_EXCM_LEVEL.
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* So that we can generate an interrupt when up_irq_save is called.
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* and not generate interrupt when up_irq_disable is called.
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* Return an error if no suitable software interrupt was found.
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*/
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#ifndef XTENSA_SWINT
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# ifdef XCHAL_SOFTWARE2_INTERRUPT
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# if XCHAL_INT_LEVEL(XCHAL_SOFTWARE2_INTERRUPT) > XCHAL_SYSCALL_LEVEL && \
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XCHAL_INT_LEVEL(XCHAL_SOFTWARE2_INTERRUPT) <= XCHAL_EXCM_LEVEL
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# undef XTENSA_SWINT
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# define XTENSA_SWINT XCHAL_SOFTWARE2_INTERRUPT
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# endif
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# endif
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# ifdef XCHAL_SOFTWARE1_INTERRUPT
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# if XCHAL_INT_LEVEL(XCHAL_SOFTWARE1_INTERRUPT) > XCHAL_SYSCALL_LEVEL && \
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XCHAL_INT_LEVEL(XCHAL_SOFTWARE1_INTERRUPT) <= XCHAL_EXCM_LEVEL
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# undef XTENSA_SWINT
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# define XTENSA_SWINT XCHAL_SOFTWARE1_INTERRUPT
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# endif
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# endif
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# ifdef XCHAL_SOFTWARE0_INTERRUPT
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# if XCHAL_INT_LEVEL(XCHAL_SOFTWARE0_INTERRUPT) > XCHAL_SYSCALL_LEVEL && \
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XCHAL_INT_LEVEL(XCHAL_SOFTWARE0_INTERRUPT) <= XCHAL_EXCM_LEVEL
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# undef XTENSA_SWINT
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# define XTENSA_SWINT XCHAL_SOFTWARE0_INTERRUPT
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# endif
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# endif
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#endif
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#ifndef XTENSA_SWINT
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# error "There is no suitable sw interrupt in this Xtensa configuration."
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#endif
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#define XCHAL_SWINT_CALL (1 << XTENSA_SWINT)
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2022-01-11 08:08:42 +01:00
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#define SYS_syscall 0x00
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2022-02-15 07:27:26 +01:00
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/* This logic uses three system calls {0,1,2} for context switching and one
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* for the syscall return. So a minimum of four syscall values must be
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2022-03-14 14:28:17 +01:00
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* reserved. If CONFIG_BUILD_FLAT isn't defined, then four more syscall
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2022-02-15 07:27:26 +01:00
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* values must be reserved.
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*/
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2016-10-12 21:11:05 +02:00
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2022-03-14 14:28:17 +01:00
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#ifndef CONFIG_BUILD_FLAT
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2022-05-11 04:47:38 +02:00
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# define CONFIG_SYS_RESERVED 9
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2022-02-25 08:40:21 +01:00
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#else
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2022-05-11 04:47:38 +02:00
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# define CONFIG_SYS_RESERVED 5
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2022-02-15 07:27:26 +01:00
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#endif
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/* Xtensa system calls ******************************************************/
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/* SYS call 0:
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*
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2022-04-20 23:50:12 +02:00
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* int up_saveusercontext(void *saveregs);
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2022-02-15 07:27:26 +01:00
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*/
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#define SYS_save_context (0)
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/* SYS call 1:
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*
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2022-04-20 23:50:12 +02:00
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* void xtensa_context_restore(uint32_t **restoreregs) noreturn_function;
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2022-02-15 07:27:26 +01:00
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*/
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#define SYS_restore_context (1)
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/* SYS call 2:
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*
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2022-04-20 23:50:12 +02:00
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* void xtensa_switchcontext(uint32_t **saveregs, uint32_t *restoreregs);
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2022-02-15 07:27:26 +01:00
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*/
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#define SYS_switch_context (2)
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2022-05-11 04:47:38 +02:00
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/* SYS call 3:
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*
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* void xtensa_flushcontext(void);
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*/
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#define SYS_flush_context (3)
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2022-02-15 07:27:26 +01:00
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#ifdef CONFIG_LIB_SYSCALL
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2022-01-11 08:08:42 +01:00
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2022-02-15 07:27:26 +01:00
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/* SYS call 3:
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*
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* void xtensa_syscall_return(void);
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*/
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2022-05-11 04:47:38 +02:00
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#define SYS_syscall_return (4)
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2022-02-24 19:46:21 +01:00
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#endif /* CONFIG_LIB_SYSCALL */
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2022-02-15 07:27:26 +01:00
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2022-02-24 19:46:21 +01:00
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#ifndef CONFIG_BUILD_FLAT
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2022-02-15 07:27:26 +01:00
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/* SYS call 4:
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*
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* void up_task_start(main_t taskentry, int argc, char *argv[])
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* noreturn_function;
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*/
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2022-05-11 04:47:38 +02:00
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#define SYS_task_start (5)
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2022-01-11 08:08:42 +01:00
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2022-02-24 19:46:21 +01:00
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/* SYS call 5:
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*
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* void up_pthread_start(pthread_trampoline_t startup,
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* pthread_startroutine_t entrypt, pthread_addr_t arg)
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* noreturn_function
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*/
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2022-05-11 04:47:38 +02:00
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#define SYS_pthread_start (6)
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2022-02-24 19:46:21 +01:00
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2022-02-15 07:27:26 +01:00
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/* SYS call 6:
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*
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* void signal_handler(_sa_sigaction_t sighand, int signo,
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* siginfo_t *info, void *ucontext);
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*/
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2022-05-11 04:47:38 +02:00
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#define SYS_signal_handler (7)
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2022-02-15 07:27:26 +01:00
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/* SYS call 7:
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*
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* void signal_handler_return(void);
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*/
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2022-05-11 04:47:38 +02:00
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#define SYS_signal_handler_return (8)
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2022-02-15 07:27:26 +01:00
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#endif /* !CONFIG_BUILD_FLAT */
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2016-10-12 21:11:05 +02:00
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/****************************************************************************
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2022-01-11 08:08:42 +01:00
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* Public Types
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****************************************************************************/
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/****************************************************************************
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* Inline functions
|
2016-10-12 21:11:05 +02:00
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****************************************************************************/
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#ifndef __ASSEMBLY__
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2022-01-11 08:08:42 +01:00
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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2016-10-12 21:11:05 +02:00
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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2022-01-11 08:08:42 +01:00
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/****************************************************************************
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* Name: sys_call0
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*
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* Description:
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* System call SYS_ argument and no additional parameters.
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*
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****************************************************************************/
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static inline uintptr_t sys_call0(unsigned int nbr)
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{
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register long reg0 __asm__("a2") = (long)(nbr);
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__asm__ __volatile__
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(
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"movi a3, %1\n"
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"wsr a3, intset\n"
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2022-03-08 10:21:02 +01:00
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"rsync\n"
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2022-01-11 08:08:42 +01:00
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: "=r"(reg0)
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: "i"(XCHAL_SWINT_CALL), "r"(reg0)
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: "a3", "memory"
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);
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return reg0;
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}
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/****************************************************************************
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* Name: sys_call1
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*
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* Description:
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* System call SYS_ argument and one additional parameter.
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*
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****************************************************************************/
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static inline uintptr_t sys_call1(unsigned int nbr, uintptr_t parm1)
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{
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register long reg0 __asm__("a2") = (long)(nbr);
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register long reg1 __asm__("a3") = (long)(parm1);
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__asm__ __volatile__
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(
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"movi a4, %1\n"
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"wsr a4, intset\n"
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2022-03-08 10:21:02 +01:00
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"rsync\n"
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2022-01-11 08:08:42 +01:00
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: "=r"(reg0)
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: "i"(XCHAL_SWINT_CALL), "r"(reg0), "r"(reg1)
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: "a4", "memory"
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);
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return reg0;
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}
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/****************************************************************************
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* Name: sys_call2
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*
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* Description:
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* System call SYS_ argument and two additional parameters.
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*
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****************************************************************************/
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static inline uintptr_t sys_call2(unsigned int nbr, uintptr_t parm1,
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uintptr_t parm2)
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{
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register long reg0 __asm__("a2") = (long)(nbr);
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register long reg2 __asm__("a4") = (long)(parm2);
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register long reg1 __asm__("a3") = (long)(parm1);
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__asm__ __volatile__
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(
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"movi a5, %1\n"
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"wsr a5, intset\n"
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2022-03-08 10:21:02 +01:00
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"rsync\n"
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2022-01-11 08:08:42 +01:00
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: "=r"(reg0)
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: "i"(XCHAL_SWINT_CALL), "r"(reg0), "r"(reg1), "r"(reg2)
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: "a5", "memory"
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);
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return reg0;
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}
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|
/****************************************************************************
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|
* Name: sys_call3
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*
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* Description:
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* System call SYS_ argument and three additional parameters.
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*
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****************************************************************************/
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static inline uintptr_t sys_call3(unsigned int nbr, uintptr_t parm1,
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uintptr_t parm2, uintptr_t parm3)
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{
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register long reg0 __asm__("a2") = (long)(nbr);
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register long reg3 __asm__("a5") = (long)(parm3);
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|
register long reg2 __asm__("a4") = (long)(parm2);
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register long reg1 __asm__("a3") = (long)(parm1);
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__asm__ __volatile__
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(
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|
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"movi a6, %1\n"
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"wsr a6, intset\n"
|
2022-03-08 10:21:02 +01:00
|
|
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"rsync\n"
|
2022-01-11 08:08:42 +01:00
|
|
|
: "=r"(reg0)
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|
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|
: "i"(XCHAL_SWINT_CALL), "r"(reg0), "r"(reg1), "r"(reg2),
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"r"(reg3)
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|
: "a6", "memory"
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|
);
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|
return reg0;
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|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: sys_call4
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* System call SYS_ argument and four additional parameters.
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
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|
|
|
|
static inline uintptr_t sys_call4(unsigned int nbr, uintptr_t parm1,
|
|
|
|
uintptr_t parm2, uintptr_t parm3,
|
|
|
|
uintptr_t parm4)
|
|
|
|
{
|
|
|
|
register long reg0 __asm__("a2") = (long)(nbr);
|
|
|
|
register long reg4 __asm__("a6") = (long)(parm4);
|
|
|
|
register long reg3 __asm__("a5") = (long)(parm3);
|
|
|
|
register long reg2 __asm__("a4") = (long)(parm2);
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|
|
|
register long reg1 __asm__("a3") = (long)(parm1);
|
|
|
|
|
|
|
|
__asm__ __volatile__
|
|
|
|
(
|
|
|
|
"movi a7, %1\n"
|
|
|
|
"wsr a7, intset\n"
|
2022-03-08 10:21:02 +01:00
|
|
|
"rsync\n"
|
2022-01-11 08:08:42 +01:00
|
|
|
: "=r"(reg0)
|
|
|
|
: "i"(XCHAL_SWINT_CALL), "r"(reg0), "r"(reg1), "r"(reg2),
|
|
|
|
"r"(reg3), "r"(reg4)
|
|
|
|
: "a7", "memory"
|
|
|
|
);
|
|
|
|
|
|
|
|
return reg0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: sys_call5
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*
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* Description:
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* System call SYS_ argument and five additional parameters.
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*
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****************************************************************************/
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static inline uintptr_t sys_call5(unsigned int nbr, uintptr_t parm1,
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uintptr_t parm2, uintptr_t parm3,
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uintptr_t parm4, uintptr_t parm5)
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{
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register long reg0 __asm__("a2") = (long)(nbr);
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register long reg5 __asm__("a7") = (long)(parm4);
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register long reg4 __asm__("a6") = (long)(parm4);
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register long reg3 __asm__("a5") = (long)(parm3);
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register long reg2 __asm__("a4") = (long)(parm2);
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register long reg1 __asm__("a3") = (long)(parm1);
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__asm__ __volatile__
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(
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"movi a8, %1\n"
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"wsr a8, intset\n"
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2022-03-08 10:21:02 +01:00
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"rsync\n"
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2022-01-11 08:08:42 +01:00
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: "=r"(reg0)
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: "i"(XCHAL_SWINT_CALL), "r"(reg0), "r"(reg1), "r"(reg2),
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"r"(reg3), "r"(reg4), "r"(reg5)
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: "a8", "memory"
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);
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return reg0;
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}
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/****************************************************************************
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* Name: sys_call6
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*
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* Description:
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* System call SYS_ argument and six additional parameters.
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*
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****************************************************************************/
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static inline uintptr_t sys_call6(unsigned int nbr, uintptr_t parm1,
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uintptr_t parm2, uintptr_t parm3,
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uintptr_t parm4, uintptr_t parm5,
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uintptr_t parm6)
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{
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register long reg0 __asm__("a2") = (long)(nbr);
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register long reg6 __asm__("a8") = (long)(parm4);
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register long reg5 __asm__("a7") = (long)(parm4);
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register long reg4 __asm__("a6") = (long)(parm4);
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register long reg3 __asm__("a5") = (long)(parm3);
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register long reg2 __asm__("a4") = (long)(parm2);
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register long reg1 __asm__("a3") = (long)(parm1);
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__asm__ __volatile__
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(
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"movi a9, %1\n"
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"wsr a9, intset\n"
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2022-03-08 10:21:02 +01:00
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"rsync\n"
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2022-01-11 08:08:42 +01:00
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: "=r"(reg0)
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: "i"(XCHAL_SWINT_CALL), "r"(reg0), "r"(reg1), "r"(reg2),
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"r"(reg3), "r"(reg4), "r"(reg5)
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: "a9", "memory"
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);
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return reg0;
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}
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2016-10-12 21:11:05 +02:00
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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2022-01-11 08:08:42 +01:00
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#endif /* __ASSEMBLY__ */
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2016-10-12 21:11:05 +02:00
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#endif /* __ARCH_XTENSA_INCLUDE_SYSCALL_H */
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