2019-08-13 18:08:49 +02:00
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/****************************************************************************
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* boards/arm/lpc17xx_40xx/mbed/include/board.h
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2010-09-10 02:37:06 +02:00
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*
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2021-03-17 18:14:12 +01:00
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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2010-09-10 02:37:06 +02:00
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*
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2021-03-17 18:14:12 +01:00
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* http://www.apache.org/licenses/LICENSE-2.0
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2010-09-10 02:37:06 +02:00
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*
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2021-03-17 18:14:12 +01:00
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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2010-09-10 02:37:06 +02:00
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*
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2019-08-13 18:08:49 +02:00
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****************************************************************************/
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2010-09-10 02:37:06 +02:00
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2019-08-13 18:08:49 +02:00
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#ifndef __BOARDS_ARM_LPC17XX_40XX_MBED_INCLUDE_BOARD_H
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#define __BOARDS_ARM_LPC17XX_40XX_MBED_INCLUDE_BOARD_H
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2010-09-10 02:37:06 +02:00
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2019-08-13 18:08:49 +02:00
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/****************************************************************************
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2010-09-10 02:37:06 +02:00
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* Included Files
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2019-08-13 18:08:49 +02:00
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****************************************************************************/
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2010-09-10 02:37:06 +02:00
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#include <nuttx/config.h>
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2019-08-13 18:08:49 +02:00
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/****************************************************************************
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2015-04-08 17:15:17 +02:00
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* Pre-processor Definitions
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2019-08-13 18:08:49 +02:00
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****************************************************************************/
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2010-09-10 02:37:06 +02:00
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2019-08-13 18:08:49 +02:00
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/* Clocking *****************************************************************/
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/* NOTE:
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* The following definitions require lpc17_40_syscon.h.
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* It is not included here because the including C file may not have that
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* file in its include path.
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2010-09-10 02:37:06 +02:00
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*/
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#define BOARD_XTAL_FREQUENCY (12000000) /* XTAL oscillator frequency */
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#define BOARD_OSCCLK_FREQUENCY BOARD_XTAL_FREQUENCY /* Main oscillator frequency */
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#define BOARD_RTCCLK_FREQUENCY (32000) /* RTC oscillator frequency */
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#define BOARD_INTRCOSC_FREQUENCY (4000000) /* Internal RC oscillator frequency */
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/* This is the clock setup we configure for:
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*
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2021-03-18 09:57:48 +01:00
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* SYSCLK = BOARD_OSCCLK_FREQUENCY = 12MHz -> Select Main oscillator for
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* source
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* PLL0CLK = (2 * 20 * SYSCLK) / 1 = 480MHz -> PLL0 multiplier=20,
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* pre-divider=1
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2019-08-13 18:08:49 +02:00
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* CCLCK = 480MHz / 6 = 80MHz -> CCLK divider = 6
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2010-09-10 02:37:06 +02:00
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*/
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2019-07-11 18:50:00 +02:00
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#define LPC17_40_CCLK 80000000 /* 80Mhz*/
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2010-09-10 02:37:06 +02:00
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2019-08-13 18:08:49 +02:00
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/* Select the main oscillator as the frequency source.
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* SYSCLK is then the frequency of the main oscillator.
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2010-09-10 02:37:06 +02:00
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*/
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2019-07-11 18:50:00 +02:00
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#undef CONFIG_LPC17_40_MAINOSC
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#define CONFIG_LPC17_40_MAINOSC 1
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2010-09-10 02:37:06 +02:00
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#define BOARD_SCS_VALUE SYSCON_SCS_OSCEN
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2019-08-13 18:08:49 +02:00
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/* Select the main oscillator and CCLK divider.
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* The output of the divider is CCLK.
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2010-09-10 02:37:06 +02:00
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* The input to the divider (PLLCLK) will be determined by the PLL output.
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*/
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#define BOARD_CCLKCFG_DIVIDER 6
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#define BOARD_CCLKCFG_VALUE ((BOARD_CCLKCFG_DIVIDER-1) << SYSCON_CCLKCFG_SHIFT)
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2019-08-13 18:08:49 +02:00
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/* PLL0.
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* PLL0 is used to generate the CPU clock divider input (PLLCLK).
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2010-09-10 02:37:06 +02:00
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*
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* Source clock: Main oscillator
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2014-04-14 00:22:22 +02:00
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* PLL0 Multiplier value (M): 20
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2010-09-10 02:37:06 +02:00
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* PLL0 Pre-divider value (N): 1
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2011-02-16 01:07:29 +01:00
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*
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* PLL0CLK = (2 * 20 * SYSCLK) / 1 = 480MHz
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2010-09-10 02:37:06 +02:00
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*/
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2019-07-11 18:50:00 +02:00
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#undef CONFIG_LPC17_40_PLL0
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#define CONFIG_LPC17_40_PLL0 1
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2010-09-10 02:37:06 +02:00
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#define BOARD_CLKSRCSEL_VALUE SYSCON_CLKSRCSEL_MAIN
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#define BOARD_PLL0CFG_MSEL 20
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#define BOARD_PLL0CFG_NSEL 1
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#define BOARD_PLL0CFG_VALUE \
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(((BOARD_PLL0CFG_MSEL-1) << SYSCON_PLL0CFG_MSEL_SHIFT) | \
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((BOARD_PLL0CFG_NSEL-1) << SYSCON_PLL0CFG_NSEL_SHIFT))
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/* PLL1 -- Not used. */
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2019-07-11 18:50:00 +02:00
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#undef CONFIG_LPC17_40_PLL1
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2010-09-10 02:37:06 +02:00
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#define BOARD_PLL1CFG_MSEL 36
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#define BOARD_PLL1CFG_NSEL 1
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#define BOARD_PLL1CFG_VALUE \
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(((BOARD_PLL1CFG_MSEL-1) << SYSCON_PLL1CFG_MSEL_SHIFT) | \
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((BOARD_PLL1CFG_NSEL-1) << SYSCON_PLL1CFG_NSEL_SHIFT))
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2019-08-13 18:08:49 +02:00
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/* USB divider.
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* This divider is used when PLL1 is not enabled to get the
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2011-02-16 01:07:29 +01:00
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* USB clock from PLL0:
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2010-09-10 02:37:06 +02:00
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*
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* USBCLK = PLL0CLK / 10 = 48MHz
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*/
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#define BOARD_USBCLKCFG_VALUE SYSCON_USBCLKCFG_DIV10
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/* FLASH Configuration */
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2019-07-11 18:50:00 +02:00
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#undef CONFIG_LPC17_40_FLASH
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#define CONFIG_LPC17_40_FLASH 1
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2010-09-10 02:37:06 +02:00
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#define BOARD_FLASHCFG_VALUE 0x0000303a
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2014-07-24 23:44:08 +02:00
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/* Ethernet configuration */
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2021-03-18 09:57:48 +01:00
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/* #define ETH_MCFG_CLKSEL_DIV ETH_MCFG_CLKSEL_DIV44 */
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2014-07-24 23:44:08 +02:00
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#define ETH_MCFG_CLKSEL_DIV ETH_MCFG_CLKSEL_DIV20
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2019-08-13 18:08:49 +02:00
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/* LED definitions **********************************************************/
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2010-09-10 02:37:06 +02:00
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/* The MBED has 4 LEDs along the bottom of the board. Blue or off.
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2019-08-13 18:08:49 +02:00
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* If CONFIG_ARCH_LEDS is defined, the LEDs will be controlled as follows
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* for NuttX debug functionality (where NC means "No Change").
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2010-09-10 02:37:06 +02:00
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*
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2019-08-13 18:08:49 +02:00
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* During the boot phases.
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* LED1 and LED2 will show boot status. LED3/4 Not used.
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2010-09-10 02:37:06 +02:00
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*/
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2021-03-18 09:57:48 +01:00
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2010-09-10 02:37:06 +02:00
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/* LED1 LED2 */
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#define LED_STARTED 0 /* OFF OFF */
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#define LED_HEAPALLOCATE 1 /* BLUE OFF */
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#define LED_IRQSENABLED 2 /* OFF BLUE */
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#define LED_STACKCREATED 3 /* OFF OFF */
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2019-08-13 18:08:49 +02:00
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/* After the system is booted, this logic will no longer use LEDs 1 & 2.
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* They are available together with LED3 for use the application software
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* using lpc17_40_led (prototyped below)
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2010-09-10 02:37:06 +02:00
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*/
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2021-03-18 09:57:48 +01:00
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/* LED1 LED2 LED3 LED4 */
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#define LED_INIRQ 4 /* NC NC NC ON (momentary) */
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#define LED_SIGNAL 5 /* NC NC NC ON (momentary) */
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2021-03-19 16:41:18 +01:00
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#define LED_ASSERTION 6 /* NC NC NC ON (momentary) */
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2021-03-18 09:57:48 +01:00
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#define LED_PANIC 7 /* NC NC NC ON (1Hz flashing) */
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2010-09-10 02:37:06 +02:00
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#define GPIO_SSP0_SCK GPIO_SSP0_SCK_1
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#define GPIO_SSP0_SSEL GPIO_SSP0_SSEL_1
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#define GPIO_SSP0_MISO GPIO_SSP0_MISO_1
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#define GPIO_SSP0_MOSI GPIO_SSP0_MOSI_1
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2011-02-16 01:07:29 +01:00
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/* We need to redefine USB_PWRD as GPIO to get USB Host working
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* Also remember to add 2 resistors of 15K to D+ and D- pins.
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*/
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#ifdef CONFIG_USBHOST
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# ifdef GPIO_USB_PWRD
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# undef GPIO_USB_PWRD
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# define GPIO_USB_PWRD (GPIO_INPUT | GPIO_PORT1 | GPIO_PIN22)
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# endif
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#endif
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2019-08-13 18:08:49 +02:00
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/* Alternate pin selections *************************************************/
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2014-07-24 23:44:08 +02:00
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/* Pin Description Connector On Board Base Board
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2019-08-13 18:08:49 +02:00
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* -------------------------------- --------- -------------- ----------------
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2014-07-24 23:44:08 +02:00
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* P0[0]/RD1/TXD3/SDA1 J6-9 I2C E2PROM SDA TXD3/SDA1
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* P0[1]/TD1/RXD3/SCL J6-10 RXD3/SCL1
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* P0[2]/TXD0/AD0[7] J6-21
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* P0[3]/RXD0/AD0[6] J6-22
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* P0[4]/I2SRX-CLK/RD2/CAP2.0 J6-38 CAN_RX2
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* P0[5]/I2SRX-WS/TD2/CAP2.1 J6-39 CAN_TX2
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* P0[6]/I2SRX_SDA/SSEL1/MAT2[0] J6-8 SSEL1, OLED CS
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* P0[7]/I2STX_CLK/SCK1/MAT2[1] J6-7 SCK1, OLED SCK
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* P0[8]/I2STX_WS/MISO1/MAT2[2] J6-6 MISO1
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2021-03-18 09:57:48 +01:00
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* P0[9]/I2STX_SDA/MOSI1/MAT2[3] J6-5 MOSI1,
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* OLED data in
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2014-07-24 23:44:08 +02:00
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* P0[10] J6-40 TXD2/SDA2
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* P0[11] J6-41 RXD2/SCL2
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* P0[15]/TXD1/SCK0/SCK J6-13 TXD1/SCK0
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* P0[16]/RXD1/SSEL0/SSEL J6-14 RXD1/SSEL0
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* P0[17]/CTS1/MISO0/MISO J6-12 MISO0
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* P0[18]/DCD1/MOSI0/MOSI J6-11 MOSI0
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* P0[19]/DSR1/SDA1 PAD17 N/A
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* P0[20]/DTR1/SCL1 PAD18 I2C E2PROM SCL N/A
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* P0[21]/RI1/MCIPWR/RD1 J6-23
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* P0[22]/RTS1/TD1 J6-24 LED
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* P0[23]/AD0[0]/I2SRX_CLK/CAP3[0] J6-15 AD0.0
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* P0[24]/AD0[1]/I2SRX_WS/CAP3[1] J6-16 AD0.1
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* P0[25]/AD0[2]/I2SRX_SDA/TXD3 J6-17 AD0.2
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2021-03-18 09:57:48 +01:00
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* P0[26]/AD0[3]/AOUT/RXD3 J6-18 AD0.3/AOUT /
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* RGB LED
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2014-07-24 23:44:08 +02:00
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* P0[27]/SDA0/USB_SDA J6-25
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* P0[28]/SCL0 J6-26
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* P0[29]/USB_D+ J6-37 USB_D+
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* P0[30]/USB_D- J6-36 USB_D-
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*/
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#define GPIO_UART3_TXD GPIO_UART3_TXD_1
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#define GPIO_I2C1_SDA GPIO_I2C1_SDA_1
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#define GPIO_UART3_RXD GPIO_UART3_RXD_1
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#define GPIO_I2C1_SCL GPIO_I2C1_SCL_1
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#define GPIO_SSP1_SCK GPIO_SSP1_SCK_1
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#define GPIO_UART2_TXD GPIO_UART2_TXD_1
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#define GPIO_UART2_RXD GPIO_UART2_RXD_1
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#define GPIO_UART1_TXD GPIO_UART1_TXD_1
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#define GPIO_SSP0_SCK GPIO_SSP0_SCK_1
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#define GPIO_UART1_RXD GPIO_UART1_RXD_1
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#define GPIO_SSP0_SSEL GPIO_SSP0_SSEL_1
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#define GPIO_SSP0_MISO GPIO_SSP0_MISO_1
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#define GPIO_SSP0_MOSI GPIO_SSP0_MOSI_1
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2021-03-18 09:57:48 +01:00
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/* P1[0]/ENET-TXD0 J6-34? TXD0 TX-
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* (Ethernet PHY)
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* P1[1]/ENET_TXD1 J6-35? TXD1 TX+
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* (Ethernet PHY)
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2014-07-24 23:44:08 +02:00
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* P1[4]/ENET_TX_EN TXEN N/A
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* P1[8]/ENET_CRS CRS_DV/MODE2 N/A
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2021-03-18 09:57:48 +01:00
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* P1[9]/ENET_RXD0 J6-32? RXD0/MODE0 RD-
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* (Ethernet PHY)
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* P1[10]/ENET_RXD1 J6-33? RXD1/MODE1 RD+
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* (Ethernet PHY)
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2014-07-24 23:44:08 +02:00
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* P1[14]/ENET_RX_ER RXER/PHYAD0 N/A
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* P1[15]/ENET_REF_CLK REFCLK N/A
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* P1[16]/ENET_MDC MDC N/A
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* P1[17]/ENET_MDIO MDIO N/A
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* P1[18]/USB_UP_LED/PWM1[1]/CAP1[0] PAD1 N/A
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* P1[19]/MC0A/USB_PPWR/N_CAP1.1 PAD2 N/A
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* P1[20]/MCFB0/PWM1.2/SCK0 PAD3 N/A
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* P1[21]/MCABORT/PWM1.3/SSEL0 PAD4 N/A
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* P1[22]/MC0B/USB-PWRD/MAT1.0 PAD5 N/A
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* P1[23]/MCFB1/PWM1.4/MISO0 PAD6 N/A
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* P1[24]/MCFB2/PWM1.5/MOSI0 PAD7 N/A
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* P1[25]/MC1A/MAT1.1 PAD8 N/A
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* P1[26]/MC1B/PWM1.6/CAP0.0 PAD9 N/A
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* P1[27]/CLKOUT/USB-OVRCR-N/CAP0.1 PAD10 N/A
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* P1[28]/MC2A/PCAP1.0/MAT0.0 PAD11 N/A
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* P1[29]/MC2B/PCAP1.1/MAT0.1 PAD12 N/A
|
|
|
|
|
* P1[30]/VBUS/AD0[4] J6-19 AD0.4
|
|
|
|
|
* P1[31]/SCK1/AD0[5] J6-20 AD0.5
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
#define GPIO_ENET_MDC GPIO_ENET_MDC_1
|
|
|
|
|
#define GPIO_ENET_MDIO GPIO_ENET_MDIO_1
|
|
|
|
|
|
2021-03-18 09:57:48 +01:00
|
|
|
/* P2[0]/PWM1.1/TXD1 J6-42 PWM1.1 /
|
|
|
|
|
* RGB LED /
|
|
|
|
|
* RS422 RX
|
|
|
|
|
* P2[1]/PWM1.2/RXD1 J6-43 PWM1.2 /
|
|
|
|
|
* OLED voltage /
|
|
|
|
|
* RGB LED /
|
|
|
|
|
* RS422 RX
|
2014-07-24 23:44:08 +02:00
|
|
|
* P2[2]/PWM1.3/CTS1/TRACEDATA[3] J6-44 PWM1.3
|
|
|
|
|
* P2[3]/PWM1.4/DCD1/TRACEDATA[2] J6-45 PWM1.4
|
|
|
|
|
* P2[4]/PWM1.5/DSR1/TRACEDATA[1] J6-46 PWM1.5
|
|
|
|
|
* P2[5]/PWM1[6]/DTR1/TRACEDATA[0] J6-47 PWM1.6
|
|
|
|
|
* P2[6]/PCAP1[0]/RI1/TRACECLK J6-48
|
2021-03-18 09:57:48 +01:00
|
|
|
* P2[7]/RD2/RTS1 J6-49 OLED cmd/data
|
2014-07-24 23:44:08 +02:00
|
|
|
* P2[8]/TD2/TXD2 J6-50
|
|
|
|
|
* P2[9]/USB_CONNECT/RXD2 PAD19 USB Pullup N/A
|
|
|
|
|
* P2[10]/EINT0/NMI J6-51
|
|
|
|
|
* P2[11]/EINT1/I2STX_CLK J6-52
|
|
|
|
|
* P2[12]/EINT2/I2STX_WS J6-53
|
|
|
|
|
* P2[13]/EINT3/I2STX_SDA J6-27
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
#define GPIO_PWM1p1 GPIO_PWM1p1_2
|
|
|
|
|
#define GPIO_PWM1p2 GPIO_PWM1p2_2
|
|
|
|
|
#define GPIO_PWM1p3 GPIO_PWM1p3_2
|
|
|
|
|
#define GPIO_PWM1p4 GPIO_PWM1p4_2
|
|
|
|
|
#define GPIO_PWM1p5 GPIO_PWM1p5_2
|
|
|
|
|
#define GPIO_PWM1p6 GPIO_PWM1p6_2
|
|
|
|
|
|
|
|
|
|
/* P3[25]/MAT0.0/PWM1.2 PAD13 N/A
|
|
|
|
|
* P3[26]/STCLK/MAT0.1/PWM1.3 PAD14 N/A
|
|
|
|
|
*
|
|
|
|
|
* P4[28]/RX-MCLK/MAT2.0/TXD3 PAD15 N/A
|
|
|
|
|
* P4[29]/TX-MCLK/MAT2.1/RXD3 PAD16 N/A
|
|
|
|
|
*/
|
|
|
|
|
|
2019-08-13 18:08:49 +02:00
|
|
|
/****************************************************************************
|
2010-09-10 02:37:06 +02:00
|
|
|
* Public Types
|
2019-08-13 18:08:49 +02:00
|
|
|
****************************************************************************/
|
2010-09-10 02:37:06 +02:00
|
|
|
|
|
|
|
|
#ifndef __ASSEMBLY__
|
|
|
|
|
|
2019-08-13 18:08:49 +02:00
|
|
|
/****************************************************************************
|
2010-09-10 02:37:06 +02:00
|
|
|
* Public Data
|
2019-08-13 18:08:49 +02:00
|
|
|
****************************************************************************/
|
2010-09-10 02:37:06 +02:00
|
|
|
|
|
|
|
|
#undef EXTERN
|
|
|
|
|
#if defined(__cplusplus)
|
|
|
|
|
#define EXTERN extern "C"
|
2014-07-24 23:44:08 +02:00
|
|
|
extern "C"
|
|
|
|
|
{
|
2010-09-10 02:37:06 +02:00
|
|
|
#else
|
|
|
|
|
#define EXTERN extern
|
|
|
|
|
#endif
|
|
|
|
|
|
2019-08-13 18:08:49 +02:00
|
|
|
/****************************************************************************
|
2010-09-10 02:37:06 +02:00
|
|
|
* Public Function Prototypes
|
2019-08-13 18:08:49 +02:00
|
|
|
****************************************************************************/
|
2010-09-10 02:37:06 +02:00
|
|
|
|
2019-08-13 18:08:49 +02:00
|
|
|
/****************************************************************************
|
2019-07-11 18:50:00 +02:00
|
|
|
* Name: lpc17_40_led
|
2010-09-10 02:37:06 +02:00
|
|
|
*
|
|
|
|
|
* Description:
|
2019-08-13 18:08:49 +02:00
|
|
|
* Once the system has booted, these functions can be used to control
|
|
|
|
|
* LEDs 1, 2 & 3
|
2010-09-10 02:37:06 +02:00
|
|
|
*
|
2019-08-13 18:08:49 +02:00
|
|
|
****************************************************************************/
|
2010-09-10 02:37:06 +02:00
|
|
|
|
|
|
|
|
#ifdef CONFIG_ARCH_LEDS
|
2019-07-11 18:50:00 +02:00
|
|
|
void lpc17_40_led(int lednum, int state);
|
2010-09-10 02:37:06 +02:00
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#undef EXTERN
|
|
|
|
|
#if defined(__cplusplus)
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#endif /* __ASSEMBLY__ */
|
2020-01-31 19:07:39 +01:00
|
|
|
#endif /* __BOARDS_ARM_LPC17XX_40XX_MBED_INCLUDE_BOARD_H */
|
