2017-05-12 16:23:16 +02:00
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#
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# For a description of the syntax of this configuration file,
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# see the file kconfig-language.txt in the NuttX tools repository.
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#
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config CAN_EXTID
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bool "CAN extended IDs"
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default n
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---help---
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Enables support for the 29-bit extended ID. Default Standard 11-bit
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IDs.
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config ARCH_HAVE_CAN_ERRORS
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bool
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default n
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config CAN_ERRORS
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bool "CAN error reporting"
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default n
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depends on ARCH_HAVE_CAN_ERRORS
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---help---
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Support CAN error reporting. If this option is selected then CAN
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error reporting is enabled. In the event of an error, the ch_error
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bit will be set in the CAN message and the following message payload
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will include a more detailed description of certain errors.
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config CAN_FD
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bool "CAN FD"
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default n
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---help---
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Enables support for the CAN_FD mode.
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config CAN_FIFOSIZE
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int "CAN driver I/O buffer size"
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default 8
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---help---
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The size of the circular buffer of CAN messages. Default: 8
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config CAN_NPENDINGRTR
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int "Number of pending RTRs"
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default 4
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---help---
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The size of the list of pending RTR requests. Default: 4
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config CAN_TXREADY
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bool "can_txready interface"
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default n
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---help---
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This selection enables the can_txready() interface. This interface
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is needed only for CAN hardware that supports queing of outgoing
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messages in a H/W FIFO.
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The CAN upper half driver also supports a queue of output messages
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in a S/W FIFO. Messages are added to that queue when when
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can_write() is called and removed from the queue in can_txdone()
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when each TX message is complete.
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After each message is added to the S/W FIFO, the CAN upper half
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driver will attempt to send the message by calling into the lower
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half driver. That send will not be performed if the lower half
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driver is busy, i.e., if dev_txready() returns false. In that
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case, the number of messages in the S/W FIFO can grow. If the
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S/W FIFO becomes full, then can_write() will wait for space in
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the S/W FIFO.
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If the CAN hardware does not support a H/W FIFO then busy means
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that the hardware is actively sending the message and is
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guaranteed to become non busy (i.e, dev_txready()) when the
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send transfer completes and can_txdone() is called. So the call
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to can_txdone() means that the transfer has completed and also
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that the hardware is ready to accept another transfer.
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If the CAN hardware supports a H/W FIFO, can_txdone() is not
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called when the tranfer is complete, but rather when the
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transfer is queued in the H/W FIFO. When the H/W FIFO becomes
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full, then dev_txready() will report false and the number of
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queued messages in the S/W FIFO will grow.
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There is no mechanism in this case to inform the upper half
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driver when the hardware is again available, when there is
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again space in the H/W FIFO. can_txdone() will not be called
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again. If the S/W FIFO becomes full, then the upper half
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driver will wait for space to become available, but there is
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no event to awaken it and the driver will hang.
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Enabling this feature adds support for the can_txready()
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interface. This function is called from the lower half
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driver's CAN interrupt handler each time a TX transfer
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completes. This is a sure indication that the H/W FIFO is
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no longer full. can_txready() will then awaken the
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can_write() logic and the hang condition is avoided.
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choice
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prompt "TX Ready Work Queue"
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default CAN_TXREADY_HIPRI
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depends on CAN_TXREADY
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config CAN_TXREADY_LOPRI
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bool "Low-priority work queue"
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select SCHED_LPWORK
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config CAN_TXREADY_HIPRI
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bool "High-priority work queue"
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select SCHED_HPWORK
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endchoice # TX Ready Work Queue
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config CAN_LOOPBACK
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bool "CAN loopback mode"
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default n
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---help---
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A CAN driver may or may not support a loopback mode for testing. If the
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driver does support loopback mode, the setting will enable it. (If the
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driver does not, this setting will have no effect).
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config CAN_NPOLLWAITERS
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int "Number of poll waiters"
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default 2
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---help---
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The maximum number of threads that may be waiting on the
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poll method.
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2017-05-23 19:28:52 +02:00
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comment "CAN Bus Controllers:"
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config CAN_MCP2515
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2017-05-23 20:22:49 +02:00
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bool "Microchip MCP2515 CAN Bus Controller over SPI"
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default n
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depends on SPI
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select ARCH_HAVE_CAN_ERRORS
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---help---
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Enable driver support for Microchip MCP2515.
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2017-05-23 19:28:52 +02:00
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if CAN_MCP2515
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config MCP2515_BITRATE
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2017-05-23 20:22:49 +02:00
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int "MCP2515 bitrate"
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default 500000
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---help---
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MCP2515 bitrate in bits per second.
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2017-05-23 19:28:52 +02:00
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config MCP2515_PROPSEG
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2017-05-23 20:22:49 +02:00
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int "MCP2515 Propagation Segment TQ"
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default 2
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range 1 8
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---help---
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The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2).
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2017-05-23 19:28:52 +02:00
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config MCP2515_PHASESEG1
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2017-05-23 20:22:49 +02:00
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int "MCP2515 Phase Segment 1"
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default 2
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range 1 8
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---help---
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The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2).
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2017-05-23 19:28:52 +02:00
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config MCP2515_PHASESEG2
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2017-05-23 20:22:49 +02:00
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int "MCP2515 Phase Segment 2"
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default 3
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range 2 8
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---help---
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The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2).
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2017-05-23 19:28:52 +02:00
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config MCP2515_SJW
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2017-05-23 20:22:49 +02:00
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int "MCP2515 Synchronization Jump Width"
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default 1
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range 1 4
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---help---
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The duration of a synchronization jump is SJW.
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2017-05-23 19:28:52 +02:00
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2019-03-20 14:49:59 +01:00
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config MCP2515_CLK_FREQUENCY
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int "MCP2515 on-board clock frequency"
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default 8000000
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range 1 25000000
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2019-04-12 19:37:08 +02:00
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config MCP2515_SPI_SCK_FREQUENCY
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int "MCP2515 SPI SCK Frequency"
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default 1000000
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range 100000 10000000
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2017-05-23 19:28:52 +02:00
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endif # CAN_MCP2515
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