109 lines
3.7 KiB
Plaintext
109 lines
3.7 KiB
Plaintext
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/****************************************************************************
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* boards/xtensa/esp32s2/esp32s2-saola-1/scripts/esp32s2.template.ld
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* ESP32S2 Linker Script Memory Layout
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*
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* This file describes the memory layout (memory blocks) as virtual
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* memory addresses.
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*
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* esp32s2.common.ld contains output sections to link compiler output
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* into these memory blocks.
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*
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* NOTE: That this is not the actual linker script but rather a "template"
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* for the elf32_out.ld script. This template script is passed through
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* the C preprocessor to include selected configuration options.
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*
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****************************************************************************/
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#include <nuttx/config.h>
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#ifdef CONFIG_ESP32S2_INSTRUCTION_CACHE_8KB
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# define CONFIG_ESP32S2_INSTRUCTION_CACHE_SIZE 0x2000
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#else
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# define CONFIG_ESP32S2_INSTRUCTION_CACHE_SIZE 0x4000
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#endif
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#ifdef CONFIG_ESP32S2_DATA_CACHE_0KB
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# define CONFIG_ESP32S2_DATA_CACHE_SIZE 0
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#elif defined CONFIG_ESP32S2_DATA_CACHE_8KB
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# define CONFIG_ESP32S2_DATA_CACHE_SIZE 0x2000
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#else
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# define CONFIG_ESP32S2_DATA_CACHE_SIZE 0x4000
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#endif
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#define RAM_IRAM_START 0x40020000
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#define RAM_DRAM_START 0x3FFB0000
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#define DATA_RAM_END 0x3FFE0000 /* 2nd stage bootloader iram_loader_seg
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* starts at SRAM block 14 (reclaimed
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* after app boots)
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*/
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#define IRAM_ORG (RAM_IRAM_START + CONFIG_ESP32S2_INSTRUCTION_CACHE_SIZE \
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+ CONFIG_ESP32S2_DATA_CACHE_SIZE)
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#define DRAM_ORG (RAM_DRAM_START + CONFIG_ESP32S2_INSTRUCTION_CACHE_SIZE \
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+ CONFIG_ESP32S2_DATA_CACHE_SIZE)
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#define I_D_RAM_SIZE DATA_RAM_END - DRAM_ORG
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#define STATIC_RAM_SIZE 0 /* FIXME: Should it be configurable? */
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MEMORY
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{
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/* All these values assume the flash cache is on, and have the blocks this
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* uses subtracted from the length of the various regions. The 'data access
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* port' dram/drom regions map to the same iram/irom regions but are
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* connected to the data port of the CPU and eg allow bytewise access.
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*/
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/* IRAM for CPU */
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iram0_0_seg (RX) : org = IRAM_ORG, len = I_D_RAM_SIZE
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/* Even though the segment name is iram, it is actually mapped to flash */
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iram0_2_seg (RX) : org = 0x40080020, len = 0x780000-0x20
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/* (0x20 offset above is a convenience for the app binary image generation.
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* Flash cache has 64KB pages. The .bin file which is flashed to the chip
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* has a 0x18 byte file header, and each segment has a 0x08 byte segment
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* header. Setting this offset makes it simple to meet the flash cache MMU's
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* constraint that (paddr % 64KB == vaddr % 64KB).)
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*/
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/* Shared data RAM, excluding memory reserved for bootloader and ROM
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* bss/data/stack.
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*/
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dram0_0_seg (RW) : org = DRAM_ORG, len = I_D_RAM_SIZE - \
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STATIC_RAM_SIZE
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/* Flash mapped constant data */
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drom0_0_seg (R) : org = 0x3f000020, len = 0x3f0000-0x20
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/* RTC fast memory (executable). Persists over deep sleep. */
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rtc_iram_seg(RWX) : org = 0x40070000, len = 0x2000
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/* RTC slow memory (data accessible). Persists over deep sleep.
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* Start of RTC slow memory is reserved for ULP co-processor code + data,
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* if enabled.
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*/
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rtc_slow_seg(RW) : org = 0x50000000 + CONFIG_ESP32S2_ULP_COPROC_RESERVE_MEM,
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len = 0x2000 - CONFIG_ESP32S2_ULP_COPROC_RESERVE_MEM
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/* External memory, including data and text */
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extmem_seg(RWX) : org = 0x3f800000, len = 0x400000
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}
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/* Heap ends at top of dram0_0_seg */
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_eheap = 0x40000000 - CONFIG_ESP32S2_TRACEMEM_RESERVE_DRAM;
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/* Module text area ends at top of dram0_0_seg */
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_emodtext = 0x400a0000;
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