2014-09-27 17:50:07 +02:00
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README.txt
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==========
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This README.txt file discusses the port of NuttX to the Intel Galileo
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board.
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NOTE: There is no port for the Galileo in place as of this writing. At this
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point in time, this README file is only a repository for pre-porting
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information. It is not clear as of this writing whether there ever will
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be a port to the Galileo development board or not.
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LEDs and Buttons
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================
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Serial Console
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==============
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Galileo provides two options for a Serial Console:
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1) UART TTL (5V/3.3V) serial communication is available on Arduino
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digital 0 (pin 1, IO0) and digital 1 (pin 2, IO1). The function of IO0
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and IO1 are controlled via a TS5A23159 2-channel 2:
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multiplexer/demultiplexer
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--- ---- --------- -------------------------------------
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PIN NAME SIGNAL DESCRIPTION
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--- ---- --------- -------------------------------------
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1 IN1 IO0_MUX Select NO1 or NC1 as IO on COM1 = IO0
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2 NO1 LVL_RXD IN=L, IO0=RXD
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3 NC1 IO0_GPIO IN=H, IO0=GPIO
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--- ---- --------- -------------------------------------
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5 IN2 IO1_MUX Select NO1 or NC1 as IO on COM2 = IO1
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4 NO2 IO1_GPIO IN=L, IO1=GPIO
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7 NC2 LVL_TXD IN=H, IO2=TXD
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--- ---- --------- -------------------------------------
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The LVL_RXD/LVL_TXD driver from UART0_TXD/UART0_RXD via a TXS0108E
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voltage level translator that brings the which brings 1.2-3.6V signals
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to 165-5.5V.
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2) In addition, a second UART provides RS-232 support via a MAX3232 driver
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2014-10-01 23:02:49 +02:00
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and is connected via a 3.5mm jack: Sleeve=GND, RING=SERIAL1_RXD, and
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2014-09-27 17:50:07 +02:00
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TIP=SERIAL1_TXD.
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UART1 may be convenient because of its built-in RS232 drivers. But if you
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have a standard RS-232 shield, then UART0 may be the better choice.
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2014-09-30 16:03:39 +02:00
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Running from SRAM
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=================
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The Host Bridge contains an interface to 512KB of on-chip, low latency,
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embedded SRAM (eSRAM). The eSRAM memory may be used as either 128 x 4KB
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pages, or in block mode as a single contiguous 512KB block page. The
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eSRAM pages may be mapped anywhere in the physical address space as a
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DRAM overlay.
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To map the eSRAM as a single 512KB block page, the register
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ESRAMPGCTRL_BLOCK is used. If any of the 4KB pages are already enabled,
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it is not possible to enable the block page.
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To map and enable the 512KB block page, the following steps should be
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followed:
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2014-10-01 23:02:49 +02:00
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- Set ESRAMPGCTRL_BLOCK.BLOCK_PG_SYSTEM_ADDRESS_16MB to the required
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address value
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2014-09-30 16:03:39 +02:00
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- Set ESRAMPGCTRL_BLOCK.BLOCK_ENABLE_PG to 1
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Once an eSRAM page is enabled, it is implicitly locked and any further
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configuration change attempts will fail.
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2014-09-27 17:50:07 +02:00
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Configurations
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==============
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