From 003511d198ac1ee68363e6d79c16d9a5ad82762b Mon Sep 17 00:00:00 2001
From: Heesub Shin <heesub.shin@samsung.com>
Date: Tue, 22 Mar 2016 15:50:12 +0900
Subject: [PATCH] ARMv7-R: add cache handling functions

This commit adds functions for enabling and disabling d/i-caches which
were missing for ARMv7-R.

Signed-off-by: Heesub Shin <heesub.shin@samsung.com>
---
 arch/arm/src/armv7-r/cache.h | 75 ++++++++++++++++++++++++++++++++++++
 1 file changed, 75 insertions(+)

diff --git a/arch/arm/src/armv7-r/cache.h b/arch/arm/src/armv7-r/cache.h
index 2c60fe2c3d..a0d25c8941 100644
--- a/arch/arm/src/armv7-r/cache.h
+++ b/arch/arm/src/armv7-r/cache.h
@@ -43,6 +43,7 @@
 #include <nuttx/config.h>
 #include <nuttx/irq.h>
 
+#include "sctlr.h"
 #include "cp15_cacheops.h"
 #include "l2cc.h"
 
@@ -50,6 +51,16 @@
  * Pre-processor Definitions
  ************************************************************************************/
 
+/* intrinsics are used in these inline functions */
+
+#define arm_isb(n) __asm__ __volatile__ ("isb " #n : : : "memory")
+#define arm_dsb(n) __asm__ __volatile__ ("dsb " #n : : : "memory")
+#define arm_dmb(n) __asm__ __volatile__ ("dmb " #n : : : "memory")
+
+#define ARM_DSB()  arm_dsb(15)
+#define ARM_ISB()  arm_isb(15)
+#define ARM_DMB()  arm_dmb(15)
+
  /************************************************************************************
  * Inline Functions
  ************************************************************************************/
@@ -183,6 +194,70 @@ static inline void arch_flush_dcache(uintptr_t start, uintptr_t end)
   l2cc_flush(start, end);
 }
 
+/****************************************************************************
+ * Name: arch_enable_icache
+ *
+ * Description:
+ *   Enable the I-Cache
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+static inline void arch_enable_icache(void)
+{
+#ifdef CONFIG_ARMV7R_ICACHE
+  uint32_t regval;
+
+  ARM_DSB();
+  ARM_ISB();
+
+  /* Enable the I-Cache */
+
+  regval = cp15_rdsctlr();
+  if ((regval & SCTLR_I) == 0)
+    {
+      cp15_wrsctlr(regval | SCTLR_I);
+    }
+
+  ARM_DSB();
+  ARM_ISB();
+#endif
+}
+
+/****************************************************************************
+* Name: arch_enable_dcache
+*
+* Description:
+*   Enable the D-Cache
+*
+* Input Parameters:
+*   None
+*
+* Returned Value:
+*   None
+*
+****************************************************************************/
+
+static inline void arch_enable_dcache(void)
+{
+#ifdef CONFIG_ARMV7R_DCACHE
+  uint32_t regval;
+
+  /* Enable the D-Cache */
+
+  regval = cp15_rdsctlr();
+  if ((regval & SCTLR_C) == 0)
+    {
+      cp15_wrsctlr(regval | SCTLR_C);
+    }
+#endif
+}
+
 /****************************************************************************
  * Public Data
  ****************************************************************************/