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esp32s3/spiflash: Fix error to pause the other CPU during operation

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Whenever a SPI flash operation will take place, it's necessary to
disable the cache and run no code from the flash. This includes
pausing the other CPU (when `CONFIG_SMP=y`). This commit prevents
an error to occur when the CPU core is evaluated before the task
is increased to the max priority.
This commit is contained in:
Tiago Medicci Serrano 2024-03-18 17:30:30 -03:00 committed by Xiang Xiao
parent 78fbc2fc64
commit 007dd34ce8
1 changed files with 8 additions and 4 deletions
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12
arch/xtensa/src/esp32s3/esp32s3_spiflash.c
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@ -285,22 +285,26 @@ static void spiflash_resume_cache(void)
static void spiflash_start(void)
{
struct tcb_s *tcb = this_task();
int cpu = up_cpu_index();
int saved_priority = tcb->sched_priority;
int cpu;
#ifdef CONFIG_SMP
int other_cpu = cpu ? 0 : 1;
int other_cpu;
#endif
nxrmutex_lock(&g_flash_op_mutex);
DEBUGASSERT(cpu == 0 || cpu == 1);
/* Temporary raise schedule priority */
nxsched_set_priority(tcb, SCHED_PRIORITY_MAX);
cpu = up_cpu_index();
#ifdef CONFIG_SMP
other_cpu = cpu == 1 ? 0 : 1;
#endif
DEBUGASSERT(cpu == 0 || cpu == 1);
#ifdef CONFIG_SMP
DEBUGASSERT(other_cpu == 0 || other_cpu == 1);
DEBUGASSERT(other_cpu != cpu);
if (OSINIT_OS_READY())