From 007dd34ce8bdf2334f6776701beb473f99fe2364 Mon Sep 17 00:00:00 2001 From: Tiago Medicci Serrano Date: Mon, 18 Mar 2024 17:30:30 -0300 Subject: [PATCH] esp32s3/spiflash: Fix error to pause the other CPU during operation Whenever a SPI flash operation will take place, it's necessary to disable the cache and run no code from the flash. This includes pausing the other CPU (when `CONFIG_SMP=y`). This commit prevents an error to occur when the CPU core is evaluated before the task is increased to the max priority. --- arch/xtensa/src/esp32s3/esp32s3_spiflash.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/xtensa/src/esp32s3/esp32s3_spiflash.c b/arch/xtensa/src/esp32s3/esp32s3_spiflash.c index f17408631f..fc943f265a 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_spiflash.c +++ b/arch/xtensa/src/esp32s3/esp32s3_spiflash.c @@ -285,22 +285,26 @@ static void spiflash_resume_cache(void) static void spiflash_start(void) { struct tcb_s *tcb = this_task(); - int cpu = up_cpu_index(); int saved_priority = tcb->sched_priority; + int cpu; #ifdef CONFIG_SMP - int other_cpu = cpu ? 0 : 1; + int other_cpu; #endif nxrmutex_lock(&g_flash_op_mutex); - DEBUGASSERT(cpu == 0 || cpu == 1); - /* Temporary raise schedule priority */ nxsched_set_priority(tcb, SCHED_PRIORITY_MAX); + cpu = up_cpu_index(); #ifdef CONFIG_SMP + other_cpu = cpu == 1 ? 0 : 1; +#endif + DEBUGASSERT(cpu == 0 || cpu == 1); + +#ifdef CONFIG_SMP DEBUGASSERT(other_cpu == 0 || other_cpu == 1); DEBUGASSERT(other_cpu != cpu); if (OSINIT_OS_READY())