From 0154e300e835a0c1dcf57b5c8b9605b9173a4805 Mon Sep 17 00:00:00 2001
From: Gregory Nutt <gnutt@nuttx.org>
Date: Tue, 12 Jul 2016 15:05:35 -0600
Subject: [PATCH] Freedom K16F: Correct calculations for SDHC clock

---
 configs/freedom-k64f/include/board.h | 29 ++++++++++++++--------------
 1 file changed, 15 insertions(+), 14 deletions(-)

diff --git a/configs/freedom-k64f/include/board.h b/configs/freedom-k64f/include/board.h
index a0da55991e..198915caa9 100644
--- a/configs/freedom-k64f/include/board.h
+++ b/configs/freedom-k64f/include/board.h
@@ -69,7 +69,7 @@
  *
  *   PLL Input frequency:   PLLIN  = REFCLK / PRDIV = 50  Mhz  / 20 = 2.5 MHz
  *   PLL Output frequency:  PLLOUT = PLLIN  * VDIV  = 2.5 Mhz  * 48 = 120 MHz
- *   MCG Frequency:         PLLOUT = 96MHz
+ *   MCG Frequency:         PLLOUT = 120 MHz
  *
  * PRDIV register value is the divider minus one.  So 20 -> 19
  * VDIV  regiser value is offset by 24.  So 28 -> 24
@@ -101,36 +101,37 @@
  *   SDCLK  frequency = (base clock) / (prescaler * divisor)
  *
  * The SDHC module is always configure configured so that the core clock is the base
- * clock.
+ * clock.  Possible values for presscaler and divisor are:
+ *
+ *   SDCLKFS: {2, 4, 8, 16, 32, 63, 128, 256}
+ *   DVS:     {1..16}
  */
 
-/* Identification mode:  400KHz = 96MHz / ( 16 * 15) */
+/* Identification mode:  Optimal 400KHz, Actual 120MHz / (32 * 10) = 375 Khz */
 
-#define BOARD_SDHC_IDMODE_PRESCALER    SDHC_SYSCTL_SDCLKFS_DIV16
-#define BOARD_SDHC_IDMODE_DIVISOR      SDHC_SYSCTL_DVS_DIV(15)
+#define BOARD_SDHC_IDMODE_PRESCALER    SDHC_SYSCTL_SDCLKFS_DIV32
+#define BOARD_SDHC_IDMODE_DIVISOR      SDHC_SYSCTL_DVS_DIV(10)
 
-/* MMC normal mode: 16MHz  = 96MHz / (2 * 3) */
+/* MMC normal mode: Optimal 20MHz, Actual 120MHz / (2 * 3) = 20 MHz */
 
 #define BOARD_SDHC_MMCMODE_PRESCALER   SDHC_SYSCTL_SDCLKFS_DIV2
 #define BOARD_SDHC_MMCMODE_DIVISOR     SDHC_SYSCTL_DVS_DIV(3)
 
-/* SD normal mode (1-bit): 16MHz  = 96MHz / (2 * 3) */
+/* SD normal mode (1-bit): Optimal 20MHz, Actual 120MHz / (2 * 3) = 20 MHz */
 
 #define BOARD_SDHC_SD1MODE_PRESCALER   SDHC_SYSCTL_SDCLKFS_DIV2
 #define BOARD_SDHC_SD1MODE_DIVISOR     SDHC_SYSCTL_DVS_DIV(3)
 
-/* SD normal mode (4-bit): 24MHz  = 96MHz / (2 * 2) (with DMA)
- * SD normal mode (4-bit): 16MHz  = 96MHz / (2 * 3) (no DMA)
+/* SD normal mode (4-bit): Optimal 25MHz, Actual 120MHz / (2 * 3) = 20 MHz (with DMA)
+ * SD normal mode (4-bit): Optimal 20MHz, Actual 120MHz / (2 * 3) = 20 MHz (no DMA)
  */
 
 #ifdef CONFIG_SDIO_DMA
 #  define BOARD_SDHC_SD4MODE_PRESCALER SDHC_SYSCTL_SDCLKFS_DIV2
-#  define BOARD_SDHC_SD4MODE_DIVISOR   SDHC_SYSCTL_DVS_DIV(2)
+#  define BOARD_SDHC_SD4MODE_DIVISOR   SDHC_SYSCTL_DVS_DIV(3)
 #else
-//#  define BOARD_SDHC_SD4MODE_PRESCALER SDHC_SYSCTL_SDCLKFS_DIV2
-//#  define BOARD_SDHC_SD4MODE_DIVISOR   SDHC_SYSCTL_DVS_DIV(3)
-#  define BOARD_SDHC_SD4MODE_PRESCALER SDHC_SYSCTL_SDCLKFS_DIV16
-#  define BOARD_SDHC_SD4MODE_DIVISOR   SDHC_SYSCTL_DVS_DIV(15)
+#  define BOARD_SDHC_SD4MODE_PRESCALER SDHC_SYSCTL_SDCLKFS_DIV2
+#  define BOARD_SDHC_SD4MODE_DIVISOR   SDHC_SYSCTL_DVS_DIV(3)
 #endif
 
 /* LED definitions ******************************************************************/