Add AHB and USB register defns for DM320
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@952 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
parent
435baccede
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019b482b89
@ -1,7 +1,7 @@
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/************************************************************************************
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* dm320/chip.h
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* arch/arm/src/dm320/chip.h
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*
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* Copyright (C) 2007 Gregory Nutt. All rights reserved.
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* Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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@ -14,7 +14,7 @@
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name Gregory Nutt nor the names of its contributors may be
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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@ -41,10 +41,12 @@
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************************************************************************************/
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#include "dm320_memorymap.h"
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#include "dm320_ahb.h"
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#include "dm320_uart.h"
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#include "dm320_timer.h"
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#include "dm320_intc.h"
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#include "dm320_gio.h"
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#include "dm320_usb.h"
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/************************************************************************************
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* Definitions
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63
arch/arm/src/dm320/dm320_ahb.h
Normal file
63
arch/arm/src/dm320/dm320_ahb.h
Normal file
@ -0,0 +1,63 @@
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/************************************************************************************
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* dm320/dm320_uart.h
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*
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* Copyright (C) 2008 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
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||||
*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_DM320_DM320_AHB_H
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#define __ARCH_ARM_SRC_DM320_DM320_AHB_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#ifndef __ASSEMBLY__
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# include <sys/types.h>
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#endif
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/************************************************************************************
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* Definitions
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************************************************************************************/
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/* AHB Bus Controller (AHBBUSC) Registers *******************************************/
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#define DM320_AHB_SDRAMSA (DM320_AHB_VADDR+0x0f00) /* SDRAM start address */
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#define DM320_AHB_SDRAMEA (DM320_AHB_VADDR+0x0f04) /* SDRAM end address */
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#define DM320_AHB_BUSCONTROL (DM320_AHB_VADDR+0x0f08) /* Bus endianess control */
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#define DM320_AHB_RSV1 (DM320_AHB_VADDR+0x0f0c) /* Reserved */
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#define DM320_AHB_USBCTL (DM320_AHB_VADDR+0x0f10) /* USB control register (ES1.1) */
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/************************************************************************************
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* Inline Functions
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************************************************************************************/
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#endif /* __ARCH_ARM_SRC_DM320_DM320_AHB_H */
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248
arch/arm/src/dm320/dm320_usb.h
Normal file
248
arch/arm/src/dm320/dm320_usb.h
Normal file
@ -0,0 +1,248 @@
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/************************************************************************************
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* dm320/dm320_uart.h
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*
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* Copyright (C) 2008 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
|
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* modification, are permitted provided that the following conditions
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* are met:
|
||||
*
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||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_DM320_DM320_USB_H
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#define __ARCH_ARM_SRC_DM320_DM320_USB_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#ifndef __ASSEMBLY__
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# include <sys/types.h>
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#endif
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/************************************************************************************
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* Definitions
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************************************************************************************/
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/* USB Controller Registers *********************************************************/
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#define DM320_USB_FADDR (DM320_USBOTG_VADDR+0x0000) /* Peripheral Address */
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#define DM320_USB_POWER (DM320_USBOTG_VADDR+0x0001) /* Power Control */
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#define DM320_USB_INTRTX1 (DM320_USBOTG_VADDR+0x0002) /* Transmit EP Interrupt Status #1 */
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#define DM320_USB_RSV1 (DM320_USBOTG_VADDR+0x0003) /* Reserved */
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#define DM320_USB_INTRRX1 (DM320_USBOTG_VADDR+0x0004) /* Receive EP Interrupt Status #1 */
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#define DM320_USB_RSV2 (DM320_USBOTG_VADDR+0x0005) /* Reserved */
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#define DM320_USB_INTRUSB (DM320_USBOTG_VADDR+0x0006) /* USB Interrupt Status */
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#define DM320_USB_INTRTX1E (DM320_USBOTG_VADDR+0x0007) /* Transmit EP Interrupt Enable #1 */
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#define DM320_USB_RSV3 (DM320_USBOTG_VADDR+0x0008) /* Reserved */
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#define DM320_USB_INTRRX1E (DM320_USBOTG_VADDR+0x0009) /* Receive EP Interrupt Enable #1 */
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#define DM320_USB_RSV4 (DM320_USBOTG_VADDR+0x000a) /* Reserved */
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#define DM320_USB_INTRUSBE (DM320_USBOTG_VADDR+0x000b) /* USB Interrupt Enable */
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#define DM320_USB_FRAME1 (DM320_USBOTG_VADDR+0x000c) /* Lower Frame Number */
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#define DM320_USB_FRAME2 (DM320_USBOTG_VADDR+0x000d) /* Upper Frame Number */
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#define DM320_USB_INDEX (DM320_USBOTG_VADDR+0x000e) /* Endpoint Index */
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#define DM320_USB_DEVCTL (DM320_USBOTG_VADDR+0x000f) /* Device Control */
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#define DM320_USB_TXMAXP (DM320_USBOTG_VADDR+0x0010) /* Transmit Maximum Packet Size */
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#define DM320_USB_PERCSR0 (DM320_USBOTG_VADDR+0x0011) /* Peripheral EP0 Control */
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#define DM320_USB_PERTXCSR1 (DM320_USBOTG_VADDR+0x0011) /* Peripheral Tx EP Control #1 */
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#define DM320_USB_CSR2 (DM320_USBOTG_VADDR+0x0012) /* EP0 Control #2 */
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#define DM320_USB_TXCSR2 (DM320_USBOTG_VADDR+0x0012) /* Tx EP Control #2 */
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#define DM320_USB_RXMAXP (DM320_USBOTG_VADDR+0x0013) /* Receive Maximum Packet Size */
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#define DM320_USB_PERRXCSR1 (DM320_USBOTG_VADDR+0x0014) /* Peripheral Rx EP Control #1 */
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#define DM320_USB_PERRXCSR2 (DM320_USBOTG_VADDR+0x0015) /* Peripheral Rx EP Control #2 */
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#define DM320_USB_COUNT0 (DM320_USBOTG_VADDR+0x0016) /* Count EP0 Data Bytes */
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#define DM320_USB_RXCOUNT1 (DM320_USBOTG_VADDR+0x0016) /* Count EP Data bytes #1 */
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#define DM320_USB_RXCOUNT2 (DM320_USBOTG_VADDR+0x0017) /* Count EP Data bytes #2 */
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#define DM320_USB_TXTYPE (DM320_USBOTG_VADDR+0x0018) /* EP Transmit Type */
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#define DM320_USB_NAKLMT0 (DM320_USBOTG_VADDR+0x0019) /* EP0 NAK Limit */
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#define DM320_USB_TXINTVL (DM320_USBOTG_VADDR+0x0019) /* EP Transmit Interval */
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#define DM320_USB_RXTYPE (DM320_USBOTG_VADDR+0x001a) /* EP Receive Type */
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#define DM320_USB_RXINTVL (DM320_USBOTG_VADDR+0x001b) /* EP Receive Interval */
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#define DM320_USB_TXFIFO1 (DM320_USBOTG_VADDR+0x001c) /* EP Transmit FIFO Address #1 */
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#define DM320_USB_TXFIFO2 (DM320_USBOTG_VADDR+0x001d) /* EP Transmit FIFO Address #2 */
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#define DM320_USB_RXFIFO1 (DM320_USBOTG_VADDR+0x001e) /* EP Receive FIFO Address #1 */
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#define DM320_USB_RXFIFO2 (DM320_USBOTG_VADDR+0x001f) /* EP Receive FIFO Address #2 */
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#define DM320_USB_HST_CSR0 (DM320_USBOTG_VADDR+0x0011) /* Host EP0 Control */
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#define DM320_USB_HSTTXCSR (DM320_USBOTG_VADDR+0x0011) /* Host Tx EP Control #1 */
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#define DM320_USB_HSTRXCSR1 (DM320_USBOTG_VADDR+0x0014) /* Host Rx EP Control #1 */
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#define DM320_USB_HSTRXCSR2 (DM320_USBOTG_VADDR+0x0015) /* Host Rx EP Control #2 */
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#define DM320_USB_FIFO0 (DM320_USBOTG_VADDR+0x0020) /* EP0 FIFO Access */
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#define DM320_USB_FIFO1 (DM320_USBOTG_VADDR+0x0024) /* EP1 FIFO Access */
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#define DM320_USB_FIFO2 (DM320_USBOTG_VADDR+0x0028) /* EP2 FIFO Access */
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#define DM320_USB_FIFO3 (DM320_USBOTG_VADDR+0x002c) /* EP3 FIFO Access */
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#define DM320_USB_FIFO4 (DM320_USBOTG_VADDR+0x0030) /* EP4 FIFO Access */
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#define DM320_USB_DMAINTR (DM320_USBOTG_VADDR+0x0200) /* Interrupt Status */
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#define DM320_USB_DMACNTL1 (DM320_USBOTG_VADDR+0x0204) /* DMA Channel1 Control */
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#define DM320_USB_DMAADDR1 (DM320_USBOTG_VADDR+0x0208) /* DMA Channel1 Address */
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#define DM320_USB_DMACOUNT1 (DM320_USBOTG_VADDR+0x020c) /* DMA Channel1 Byte Count */
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#define DM320_USB_DMACNTL2 (DM320_USBOTG_VADDR+0x0214) /* DMA Channel2 Control */
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#define DM320_USB_DMAADDR2 (DM320_USBOTG_VADDR+0x0218) /* DMA Channel2 Address */
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#define DM320_USB_DMACOUNT2 (DM320_USBOTG_VADDR+0x021c) /* DMA Channel2 Byte Count */
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#define DM320_USB_DMACNTL3 (DM320_USBOTG_VADDR+0x0224) /* DMA Channel3 Control */
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#define DM320_USB_DMAADDR3 (DM320_USBOTG_VADDR+0x0228) /* DMA Channel3 Address */
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#define DM320_USB_DMACOUNT3 (DM320_USBOTG_VADDR+0x022c) /* DMA Channel3 Byte Count */
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#define DM320_USB_DMACNTL4 (DM320_USBOTG_VADDR+0x0234) /* DMA Channel4 Control */
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#define DM320_USB_DMAADDR4 (DM320_USBOTG_VADDR+0x0238) /* DMA Channel4 Address */
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#define DM320_USB_DMACOUNT4 (DM320_USBOTG_VADDR+0x023c) /* DMA Channel4 Byte Count */
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/* POWER register bit settings ******************************************************/
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#define USB_POWER_ENSUS (0x00000001)
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#define USB_POWER_SUSPEND (0x00000002)
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#define USB_POWER_RESUME (0x00000004)
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#define USB_POWER_RESET (0x00000008)
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#define USB_POWER_VBUSLO (0x00000010)
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#define USB_POWER_VBUSSESS (0x00000020)
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#define USB_POWER_VBUSVAL (0x00000040)
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#define USB_POWER_ISO (0x00000080)
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/* USB interrupt bits **************************************************************/
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#define USB_INT_NOINTERRUPT (0x00000000)
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#define USB_INT_SUSPEND (0x00000001)
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#define USB_INT_RESUME (0x00000002)
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#define USB_INT_RESET (0x00000004)
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#define USB_INT_SOF (0x00000008)
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#define USB_INT_CONNECTED (0x00000010)
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#define USB_INT_DISCONNECTED (0x00000020)
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#define USB_INT_SESSRQ (0x00000040)
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#define USB_INT_VBUSERR (0x00000080)
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#define USB_INT_RXFIFO (0x00000f00)
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#define USB_INT_RXFIFO1 (0x00000100)
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#define USB_INT_RXFIFO2 (0x00000200)
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#define USB_INT_RXFIFO3 (0x00000400)
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#define USB_INT_RXFIFO4 (0x00000800)
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#define USB_INT_CONTROL (0x00001000)
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#define USB_INT_TXFIFO (0x0001e000)
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#define USB_INT_TXFIFO1 (0x00002000)
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#define USB_INT_TXFIFO2 (0x00004000)
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#define USB_INT_TXFIFO3 (0x00008000)
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#define USB_INT_TXFIFO4 (0x00010000)
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#define USB_EP4_TX (0x10)
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#define USB_EP3_TX (0x08)
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#define USB_EP2_TX (0x04)
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#define USB_EP1_TX (0x02)
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#define USB_EP0 (0x01)
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#define USB_EP4_RX (0x10)
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#define USB_EP3_RX (0x08)
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#define USB_EP2_RX (0x04)
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#define USB_EP1_RX (0x02)
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/* Endpoint control register index *************************************************/
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#define USB_EP0_SELECT (0x00)
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/* DEVCTL register bit settings ****************************************************/
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#define USB_DEVCTL_CID (0x80)
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#define USB_DEVCTL_FSDEV (0x40)
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#define USB_DEVCTL_LSDEV (0x20)
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#define USB_DEVCTL_PUCON (0x10)
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#define USB_DEVCTL_PDCON (0x08)
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#define USB_DEVCTL_MODE (0x04)
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#define USB_DEVCTL_HOSTREQ (0x02)
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#define USB_DEVCTL_SESSREQ (0x01)
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/* PERCSR0 register bit settings ***************************************************/
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#define USB_PERCSR0_CLRSETEND (0x80)
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#define USB_PERCSR0_CLRRXRDY (0x40)
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#define USB_PERCSR0_SENDST (0x20)
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#define USB_PERCSR0_SETEND (0x10)
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#define USB_PERCSR0_DATAEND (0x08)
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#define USB_PERCSR0_SENTST (0x04)
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#define USB_PERCSR0_TXPKTRDY (0x02)
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#define USB_PERCSR0_RXPKTRDY (0x01)
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/* TXCSR1 register bit settings ****************************************************/
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#define USB_TXCSR1_CLRDATTOG (0x40)
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#define USB_TXCSR1_SENTST (0x20)
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#define USB_TXCSR1_SENDST (0x10)
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#define USB_TXCSR1_FLFIFO (0x08)
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#define USB_TXCSR1_UNDERRUN (0x04)
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#define USB_TXCSR1_FIFOEMP (0x02)
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#define USB_TXCSR1_TXPKTRDY (0x01)
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/* CSR2 register bit settings ******************************************************/
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#define USB_CSR2_FLFIFO (0x01)
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/* TXCSR2 register bit settings ****************************************************/
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#define USB_TXCSR2_AUTOSET (0x80)
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#define USB_TXCSR2_ISO (0x40)
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#define USB_TXCSR2_MODE_TX (0x20)
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#define USB_TXCSR2_DMAEN (0x10)
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#define USB_TXCSR2_FRDATTOG (0x08)
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#define USB_TXCSR2_DMAMODE1 (0x04)
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/* PERRXCSR1 register bit settings *************************************************/
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#define USB_PERRXCSR1_CLRDATTOG (0x80)
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#define USB_PERRXCSR1_SENTST (0x40)
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#define USB_PERRXCSR1_SENDST (0x20)
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#define USB_PERRXCSR1_FLFIFO (0x10)
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#define USB_PERRXCSR1_DATERR (0x08)
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#define USB_PERRXCSR1_OVERRUN (0x04)
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#define USB_PERRXCSR1_FIFOFUL (0x02)
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#define USB_PERRXCSR1_RXPKTRDY (0x01)
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/* PERRXCSR2 register bit settings *************************************************/
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#define USB_PERPXCSR2_AUTOCLR (0x80)
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#define USB_PERPXCSR2_ISO (0x40)
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#define USB_PERPXCSR2_DMAEN (0x20)
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#define USB_PERPXCSR2_DMAMODE1 (0x10)
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/* TXFIFO2 register bit settings **************************************************/
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#define USB_TXFIFO2_SZ_8 (0x00)
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#define USB_TXFIFO2_SZ_16 (0x20)
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#define USB_TXFIFO2_SZ_32 (0x40)
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#define USB_TXFIFO2_SZ_64 (0x60)
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#define USB_TXFIFO2_SZ_128 (0x80)
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#define USB_TXFIFO2_SZ_256 (0xa0)
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#define USB_TXFIFO2_SZ_512 (0xc0)
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#define USB_TXFIFO2_SZ_1024 (0xe0)
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#define USB_TXFIFO2_SINGLE_BUF (0x00)
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#define USB_TXFIFO2_DOUBLE_BUF (0x10)
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/* USBDMA control register bit settings ********************************************/
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#define USBDMA_CNTL_DMAEN (0x01)
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#define USBDMA_CNTL_DIR_IN (0x02)
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#define USBDMA_CNTL_DMAMODE1 (0x04)
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#define USBDMA_CNTL_INTREN (0x08)
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/************************************************************************************
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* Inline Functions
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************************************************************************************/
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||||
#endif /* __ARCH_ARM_SRC_DM320_DM320_USB_H */
|
||||
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