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arch/arm/src/stm32: introduce DBGMCU IP core versions

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This commit is contained in:
raiden00pl 2021-04-10 20:52:31 +02:00 committed by Xiang Xiao
parent 3caf26fe3e
commit 021a89569d
2 changed files with 18 additions and 4 deletions
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14
arch/arm/src/stm32/Kconfig
View File

@ -1297,6 +1297,7 @@ config STM32_STM32L15XX
select STM32_HAVE_ADC2
select STM32_HAVE_USART3
select STM32_HAVE_RTC_SUBSECONDS if !STM32_LOWDENSITY
select STM32_HAVE_IP_DBGMCU_V2
select STM32_HAVE_IP_TIMERS_V1
select STM32_HAVE_IP_ADC_V1
select STM32_HAVE_IP_DMA_V1
@ -1316,6 +1317,7 @@ config STM32_STM32F10XX
select STM32_HAVE_SPI3 if STM32_HIGHDENSITY || STM32_MEDIUMDENSITY
select STM32_HAVE_RTC_COUNTER
select STM32_HAVE_TIM3
select STM32_HAVE_IP_DBGMCU_V1
select STM32_HAVE_IP_TIMERS_V1
select STM32_HAVE_IP_ADC_V1_BASIC
select STM32_HAVE_IP_DMA_V1
@ -1467,6 +1469,7 @@ config STM32_STM32F20XX
select STM32_HAVE_SPI2
select STM32_HAVE_SPI3
select STM32_HAVE_IOCOMPENSATION
select STM32_HAVE_IP_DBGMCU_V2
select STM32_HAVE_IP_TIMERS_V1
select STM32_HAVE_IP_ADC_V1
select STM32_HAVE_IP_DMA_V2
@ -1497,6 +1500,7 @@ config STM32_STM32F30XX
select STM32_HAVE_TIM16
select STM32_HAVE_TIM17
select STM32_HAVE_TSC
select STM32_HAVE_IP_DBGMCU_V2
select STM32_HAVE_IP_TIMERS_V2
select STM32_HAVE_IP_ADC_V2
select STM32_HAVE_IP_DMA_V1
@ -1546,6 +1550,7 @@ config STM32_STM32F33XX
select STM32_HAVE_DAC1
select STM32_HAVE_DAC2
select STM32_HAVE_USART3
select STM32_HAVE_IP_DBGMCU_V2
select STM32_HAVE_IP_TIMERS_V2
select STM32_HAVE_IP_ADC_V2
select STM32_HAVE_IP_DMA_V1
@ -1592,6 +1597,7 @@ config STM32_STM32F4XXX
select STM32_HAVE_SPI2
select STM32_HAVE_I2C2
select STM32_HAVE_IOCOMPENSATION
select STM32_HAVE_IP_DBGMCU_V2
select STM32_HAVE_IP_TIMERS_V1
select STM32_HAVE_IP_ADC_V1
select STM32_HAVE_IP_DMA_V2
@ -2538,6 +2544,14 @@ config STM32_HAVE_OPAMP6
# These are STM32 peripherals IP blocks
config STM32_HAVE_IP_DBGMCU_V1
bool
default n
config STM32_HAVE_IP_DBGMCU_V2
bool
default n
config STM32_HAVE_IP_I2C_V1
bool
default n

8
arch/arm/src/stm32/hardware/stm32_dbgmcu.h
View File

@ -37,9 +37,7 @@
#define STM32_DBGMCU_IDCODE 0xe0042000 /* MCU identifier */
#define STM32_DBGMCU_CR 0xe0042004 /* MCU debug */
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \
defined(CONFIG_STM32_STM32F33XX) || defined(CONFIG_STM32_STM32F4XXX) || \
defined(CONFIG_STM32_STM32L15XX)
#ifdef CONFIG_STM32_HAVE_IP_DBGMCU_V2
# define STM32_DBGMCU_APB1_FZ 0xe0042008 /* Debug MCU APB1 freeze register */
# define STM32_DBGMCU_APB2_FZ 0xe004200c /* Debug MCU APB2 freeze register */
#endif
@ -67,7 +65,7 @@
# define DBGMCU_CR_SYNCH2 (2 << DBGMCU_CR_TRACEMODE_SHIFT) /* Synchronous Mode, TRACEDATA size=2 */
# define DBGMCU_CR_SYNCH4 (3 << DBGMCU_CR_TRACEMODE_SHIFT) /* Synchronous Mode, TRACEDATA size=4 */
#ifdef CONFIG_STM32_STM32F10XX
#ifdef CONFIG_STM32_HAVE_IP_DBGMCU_V1
# define DBGMCU_CR_IWDGSTOP (1 << 8) /* Bit 8: Independent Watchdog stopped when core is halted */
# define DBGMCU_CR_WWDGSTOP (1 << 9) /* Bit 9: Window Watchdog stopped when core is halted */
# define DBGMCU_CR_TIM1STOP (1 << 10) /* Bit 10: TIM1 stopped when core is halted */
@ -86,6 +84,7 @@
/* Debug MCU APB1 freeze register */
#ifdef CONFIG_STM32_HAVE_IP_DBGMCU_V2
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
# define DBGMCU_APB1_TIM2STOP (1 << 0) /* Bit 0: TIM2 stopped when core is halted */
# define DBGMCU_APB1_TIM3STOP (1 << 1) /* Bit 1: TIM3 stopped when core is halted */
@ -140,6 +139,7 @@
# define DBGMCU_APB2_TIM10STOP (1 << 3) /* Bit 3: TIM10 stopped when core is halted */
# define DBGMCU_APB2_TIM11STOP (1 << 4) /* Bit 4: TIM11 stopped when core is halted */
#endif
#endif
/****************************************************************************
* Public Types