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BL808: Add support for UARTs 0-2 and serial configuration

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This commit modifies the existing serial driver to add support for the remaining UARTs on the BL808. It also introduces support for setting baud rate, character length, stop bits, parity, flow control and which serial port acts as the console.
This commit is contained in:
Henry Rovner 2024-06-20 15:04:29 -07:00 committed by Xiang Xiao
parent 126c83a7dc
commit 023bd08faa
6 changed files with 368 additions and 8 deletions
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18
arch/risc-v/src/bl808/Kconfig
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@ -7,6 +7,24 @@ comment "BL808 Configuration Options"
menu "BL808 Peripheral Support"
config BL808_UART0
bool "UART 0"
default n
select UART0_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
config BL808_UART1
bool "UART 1"
default n
select UART1_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
config BL808_UART2
bool "UART 2"
default n
select UART2_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
config BL808_UART3
bool "UART 3"
default n

254
arch/risc-v/src/bl808/bl808_serial.c
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@ -39,6 +39,7 @@
#include <nuttx/serial/tioctl.h>
#include "hardware/bl808_uart.h"
#include "hardware/bl808_glb.h"
#include "riscv_internal.h"
#include "chip.h"
#include "bl808_serial.h"
@ -47,7 +48,15 @@
* Pre-processor Definitions
****************************************************************************/
#if defined(CONFIG_UART0_SERIAL_CONSOLE)
#define CONSOLE_DEV g_uart0port /* UART0 is console */
#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
#define CONSOLE_DEV g_uart1port /* UART1 is console */
#elif defined(CONFIG_UART2_SERIAL_CONSOLE)
#define CONSOLE_DEV g_uart2port /* UART2 is console */
#elif defined(CONFIG_UART3_SERIAL_CONSOLE)
#define CONSOLE_DEV g_uart3port /* UART3 is console */
#endif
/****************************************************************************
* Private Types
@ -114,9 +123,161 @@ static const struct uart_ops_s g_uart_ops =
/* I/O buffers */
static char g_uart0rxbuffer[CONFIG_UART0_RXBUFSIZE];
static char g_uart0txbuffer[CONFIG_UART0_TXBUFSIZE];
static char g_uart1rxbuffer[CONFIG_UART1_RXBUFSIZE];
static char g_uart1txbuffer[CONFIG_UART1_TXBUFSIZE];
static char g_uart2rxbuffer[CONFIG_UART2_RXBUFSIZE];
static char g_uart2txbuffer[CONFIG_UART2_TXBUFSIZE];
static char g_uart3rxbuffer[CONFIG_UART3_RXBUFSIZE];
static char g_uart3txbuffer[CONFIG_UART3_TXBUFSIZE];
/* UART port structs */
static struct bl808_uart_s g_uart0priv =
{
.irq = BL808_IRQ_UART0,
.config =
{
.idx = 0,
.baud = CONFIG_UART0_BAUD,
.parity = CONFIG_UART0_PARITY,
.data_bits = CONFIG_UART0_BITS,
.stop_bits = CONFIG_UART0_2STOP,
#ifdef CONFIG_UART0_IFLOWCONTROL
.iflow_ctl = CONFIG_UART0_IFLOWCONTROL,
#else
.iflow_ctl = 0,
#endif
#ifdef CONFIG_UART0_OFLOWCONTROL
.oflow_ctl = CONFIG_UART0_OFLOWCONTROL,
#else
.oflow_ctl = 0,
#endif
},
};
static uart_dev_t g_uart0port =
{
#ifdef CONFIG_UART0_SERIAL_CONSOLE
.isconsole = 1,
#else
.isconsole = 0,
#endif
.recv =
{
.size = CONFIG_UART0_RXBUFSIZE,
.buffer = g_uart0rxbuffer,
},
.xmit =
{
.size = CONFIG_UART0_TXBUFSIZE,
.buffer = g_uart0txbuffer,
},
.ops = &g_uart_ops,
.priv = (void *)&g_uart0priv,
};
static struct bl808_uart_s g_uart1priv =
{
.irq = BL808_IRQ_UART1,
.config =
{
.idx = 1,
.baud = CONFIG_UART1_BAUD,
.parity = CONFIG_UART1_PARITY,
.data_bits = CONFIG_UART1_BITS,
.stop_bits = CONFIG_UART1_2STOP,
#ifdef CONFIG_UART1_IFLOWCONTROL
.iflow_ctl = CONFIG_UART1_IFLOWCONTROL,
#else
.iflow_ctl = 0,
#endif
#ifdef CONFIG_UART1_OFLOWCONTROL
.oflow_ctl = CONFIG_UART1_OFLOWCONTROL,
#else
.oflow_ctl = 0,
#endif
},
};
static uart_dev_t g_uart1port =
{
#ifdef CONFIG_UART1_SERIAL_CONSOLE
.isconsole = 1,
#else
.isconsole = 0,
#endif
.recv =
{
.size = CONFIG_UART1_RXBUFSIZE,
.buffer = g_uart1rxbuffer,
},
.xmit =
{
.size = CONFIG_UART1_TXBUFSIZE,
.buffer = g_uart1txbuffer,
},
.ops = &g_uart_ops,
.priv = (void *)&g_uart1priv,
};
static struct bl808_uart_s g_uart2priv =
{
.irq = BL808_IRQ_UART2,
.config =
{
.idx = 2,
.baud = CONFIG_UART2_BAUD,
.parity = CONFIG_UART2_PARITY,
.data_bits = CONFIG_UART2_BITS,
.stop_bits = CONFIG_UART2_2STOP,
#ifdef CONFIG_UART2_IFLOWCONTROL
.iflow_ctl = CONFIG_UART2_IFLOWCONTROL,
#else
.iflow_ctl = 0,
#endif
#ifdef CONFIG_UART2_OFLOWCONTROL
.oflow_ctl = CONFIG_UART2_OFLOWCONTROL,
#else
.oflow_ctl = 0,
#endif
},
};
static uart_dev_t g_uart2port =
{
#ifdef CONFIG_UART2_SERIAL_CONSOLE
.isconsole = 1,
#else
.isconsole = 0,
#endif
.recv =
{
.size = CONFIG_UART2_RXBUFSIZE,
.buffer = g_uart2rxbuffer,
},
.xmit =
{
.size = CONFIG_UART2_TXBUFSIZE,
.buffer = g_uart2txbuffer,
},
.ops = &g_uart_ops,
.priv = (void *)&g_uart2priv,
};
static struct bl808_uart_s g_uart3priv =
{
.irq = BL808_IRQ_UART3,
@ -144,7 +305,12 @@ static struct bl808_uart_s g_uart3priv =
static uart_dev_t g_uart3port =
{
#ifdef CONFIG_UART3_SERIAL_CONSOLE
.isconsole = 1,
#else
.isconsole = 0,
#endif
.recv =
{
.size = CONFIG_UART3_RXBUFSIZE,
@ -161,7 +327,10 @@ static uart_dev_t g_uart3port =
static struct uart_dev_s *const g_uart_devs[] =
{
[0] = &g_uart3port,
[0] = &g_uart0port,
[1] = &g_uart1port,
[2] = &g_uart2port,
[3] = &g_uart3port
};
/****************************************************************************
@ -233,7 +402,74 @@ static int __uart_interrupt(int irq, void *context, void *arg)
static void bl808_uart_configure(const struct uart_config_s *config)
{
/* Assume that U-Boot Bootloader has already configured the UART */
uint8_t uart_idx = config->idx;
/* UTX_CONFIG */
uint32_t tmp_val = getreg32(BL808_UART_UTX_CONFIG(uart_idx));
tmp_val &= ~UART_UTX_CONFIG_CR_BIT_CNT_P_MASK;
if (config->stop_bits)
{
tmp_val |= 3 << UART_UTX_CONFIG_CR_BIT_CNT_P_SHIFT;
}
else
{
tmp_val |= 1 << UART_UTX_CONFIG_CR_BIT_CNT_P_SHIFT;
}
tmp_val &= ~UART_UTX_CONFIG_CR_BIT_CNT_D_MASK;
tmp_val |= config->data_bits << UART_UTX_CONFIG_CR_BIT_CNT_D_SHIFT;
switch (config->parity)
{
case 0:
tmp_val &= ~UART_UTX_CONFIG_CR_PRT_EN;
break;
case 1:
tmp_val |= UART_UTX_CONFIG_CR_PRT_EN;
tmp_val |= UART_UTX_CONFIG_CR_PRT_SEL;
break;
case 2:
tmp_val |= UART_UTX_CONFIG_CR_PRT_EN;
tmp_val &= ~UART_UTX_CONFIG_CR_PRT_SEL;
break;
}
tmp_val |= UART_UTX_CONFIG_CR_FRM_EN;
if (config->oflow_ctl)
{
tmp_val |= UART_UTX_CONFIG_CR_CTS_EN;
}
else
{
tmp_val &= ~UART_UTX_CONFIG_CR_CTS_EN;
}
tmp_val |= UART_UTX_CONFIG_CR_EN;
putreg32(tmp_val, BL808_UART_UTX_CONFIG(uart_idx));
/* URX CONFIG */
tmp_val = getreg32(BL808_UART_URX_CONFIG(uart_idx));
tmp_val |= UART_URX_CONFIG_CR_EN;
putreg32(tmp_val, BL808_UART_URX_CONFIG(uart_idx));
/* BIT PRD (baud rate) */
uint16_t div = BL808_UART_CLK / config->baud - 1;
tmp_val = getreg32(BL808_UART_BIT_PRD(uart_idx));
tmp_val = div | (div << 16);
putreg32(tmp_val, BL808_UART_BIT_PRD(uart_idx));
/* FIFO CONFIG 1 */
tmp_val = getreg32(BL808_UART_FIFO_CONFIG_1(uart_idx));
tmp_val |= 1 << UART_FIFO_CONFIG_1_TX_TH_SHIFT;
putreg32(tmp_val, BL808_UART_FIFO_CONFIG_1(uart_idx));
}
/****************************************************************************
@ -770,7 +1006,8 @@ void bl808_serialinit(void)
int up_putc(int ch)
{
struct uart_dev_s *priv = CONSOLE_DEV.priv;
struct bl808_uart_s *priv = CONSOLE_DEV.priv;
uint8_t uart_idx = priv->config.idx;
irqstate_t flags = enter_critical_section();
/* Check for LF */
@ -779,10 +1016,17 @@ int up_putc(int ch)
{
/* Add CR */
bl808_send(priv, '\r');
while ((getreg32(BL808_UART_FIFO_CONFIG_1(uart_idx)) &
UART_FIFO_CONFIG_1_TX_CNT_MASK) == 0);
putreg32('\r', BL808_UART_FIFO_WDATA(uart_idx));
}
bl808_send(priv, ch);
while ((getreg32(BL808_UART_FIFO_CONFIG_1(uart_idx)) &
UART_FIFO_CONFIG_1_TX_CNT_MASK) == 0);
putreg32(ch, BL808_UART_FIFO_WDATA(uart_idx));
leave_critical_section(flags);
return ch;
}

69
arch/risc-v/src/bl808/hardware/bl808_glb.h Normal file
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@ -0,0 +1,69 @@
/****************************************************************************
* arch/risc-v/src/bl808/hardware/bl808_glb.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISCV_SRC_BL808_HARDWARE_BL808_GLB_H
#define __ARCH_RISCV_SRC_BL808_HARDWARE_BL808_GLB_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "bl808_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define BL808_GLB_UART_CFG1_OFFSET 0x154
#define BL808_GLB_UART_CFG2_OFFSET 0x158
#define BL808_GPIO_CFG_OFFSET 0x0008c4 /* gpio_cfg0 */
/* Register definitions *****************************************************/
#define BL808_GLB_UART_CFG1 (BL808_GLB_BASE + BL808_GLB_UART_CFG1_OFFSET)
#define BL808_GLB_UART_CFG2 (BL808_GLB_BASE + BL808_GLB_UART_CFG2_OFFSET)
#define BL808_GPIO_CFG(n) (BL808_GLB_BASE + BL808_GPIO_CFG_OFFSET + 4*n)
/* Register bit definitions *************************************************/
/* UART_CFG registers *******************************************************/
#define UART_CFG_SIG_SEL_SHIFT(n) ((n % 8) * 4)
#define UART_CFG_SIG_SEL_MASK(n) (0x0f << UART_CFG_SIG_SEL_SHIFT(n))
/* GPIO_CFG registers *******************************************************/
/* bit definitions from lupyuen's wip-nuttx, branch gpio2 *******************/
#define GPIO_CFGCTL0_GPIO_0_FUNC_SEL_SHIFT (8)
#define GPIO_CFGCTL0_GPIO_0_FUNC_SEL_MASK (0x0f << GPIO_CFGCTL0_GPIO_0_FUNC_SEL_SHIFT)
#define GPIO_CFGCTL0_GPIO_0_OE (1 << 6)
#define GPIO_CFGCTL0_GPIO_0_PD (1 << 5)
#define GPIO_CFGCTL0_GPIO_0_PU (1 << 4)
#define GPIO_CFGCTL0_GPIO_0_DRV_SHIFT (2)
#define GPIO_CFGCTL0_GPIO_0_DRV_MASK (0x03 << GPIO_CFGCTL0_GPIO_0_DRV_SHIFT)
#define GPIO_CFGCTL0_GPIO_0_SMT (1 << 1)
#define GPIO_CFGCTL0_GPIO_0_IE (1 << 0)
#endif /* __ARCH_RISCV_SRC_BL808_HARDWARE_BL808_GLB_H */

5
arch/risc-v/src/bl808/hardware/bl808_memorymap.h
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@ -27,6 +27,11 @@
/* Register Base Address ****************************************************/
#define BL808_GLB_BASE 0x20000000ul
#define BL808_UART0_BASE 0x2000a000ul
#define BL808_UART1_BASE 0x2000a100ul
#define BL808_UART2_BASE 0x2000aa00ul
#define BL808_UART3_BASE 0x30002000ul
#define IPC0_BASE 0x2000a800ul

9
arch/risc-v/src/bl808/hardware/bl808_uart.h
View File

@ -32,9 +32,12 @@
* Pre-processor Definitions
****************************************************************************/
/* Only UART3 is supported */
#define BL808_UART_CLK 40000000
#define BL808_UART_BASE(n) (UNUSED(n), BL808_UART3_BASE)
#define BL808_UART_BASE(n) ((n == 0) ? BL808_UART0_BASE \
: (n == 1) ? BL808_UART1_BASE \
: (n == 2) ? BL808_UART2_BASE \
: BL808_UART3_BASE)
/* Register offsets *********************************************************/
@ -80,7 +83,7 @@
#define UART_UTX_CONFIG_CR_LEN_SHIFT (16)
#define UART_UTX_CONFIG_CR_LEN_MASK (0xffff << UART_UTX_CONFIG_CR_LEN_SHIFT)
#define UART_UTX_CONFIG_CR_BIT_CNT_P_SHIFT (12)
#define UART_UTX_CONFIG_CR_BIT_CNT_P_SHIFT (11)
#define UART_UTX_CONFIG_CR_BIT_CNT_P_MASK (0x03 << UART_UTX_CONFIG_CR_BIT_CNT_P_SHIFT)
#define UART_UTX_CONFIG_CR_BIT_CNT_D_SHIFT (8)
#define UART_UTX_CONFIG_CR_BIT_CNT_D_MASK (0x07 << UART_UTX_CONFIG_CR_BIT_CNT_D_SHIFT)

21
boards/risc-v/bl808/ox64/configs/nsh/defconfig
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@ -31,6 +31,9 @@ CONFIG_ARCH_TEXT_VBASE=0x80000000
CONFIG_ARCH_USE_MMU=y
CONFIG_ARCH_USE_MPU=y
CONFIG_ARCH_USE_S_MODE=y
CONFIG_BL808_UART0=y
CONFIG_BL808_UART1=y
CONFIG_BL808_UART2=y
CONFIG_BL808_UART3=y
CONFIG_BOARDCTL_ROMDISK=y
CONFIG_BOARD_LATE_INITIALIZE=y
@ -81,6 +84,24 @@ CONFIG_SYSTEM_NSH=y
CONFIG_SYSTEM_NSH_PROGNAME="init"
CONFIG_TESTING_GETPRIME=y
CONFIG_TESTING_OSTEST=y
CONFIG_UART0_BAUD=2000000
CONFIG_UART0_SERIAL_CONSOLE=y
CONFIG_UART0_PARITY=0
CONFIG_UART0_BITS=7
CONFIG_UART0_2STOP=0
CONFIG_UART1_BAUD=2000000
CONFIG_UART1_SERIAL_DRIVER=y
CONFIG_UART1_PARITY=0
CONFIG_UART1_BITS=7
CONFIG_UART1_2STOP=0
CONFIG_UART2_BAUD=2000000
CONFIG_UART2_SERIAL_DRIVER=y
CONFIG_UART2_PARITY=0
CONFIG_UART2_BITS=7
CONFIG_UART2_2STOP=0
CONFIG_UART3_BAUD=2000000
CONFIG_UART3_SERIAL_CONSOLE=y
CONFIG_UART3_PARITY=0
CONFIG_UART3_BITS=7
CONFIG_UART3_2STOP=0
CONFIG_USEC_PER_TICK=1000