More PIC32 debug updates
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4083 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
parent
ceaff95d18
commit
02459d0d1f
@ -76,7 +76,7 @@
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# define CONFIG_ARCH_INTERRUPTSTACK 0
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#endif
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/* In the MIPS model, the state is copied from the stack to the TCB, but
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/* In the MIPS model, the state is copied from the stack to the TCB, but
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* only a referenced is passed to get the state from the TCB.
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*/
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@ -182,6 +182,10 @@ extern void up_dumpstate(void);
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extern uint32_t *up_doirq(int irq, uint32_t *regs);
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/* Software interrupt 0 handler */
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extern int up_swint0(int irq, FAR void *context);
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/* Signals */
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extern void up_sigdeliver(void);
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@ -326,7 +326,7 @@ int up_swint0(int irq, FAR void *context)
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case SYS_switch_context:
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{
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DEBUGASSERT(regs[REG_A1] != 0 && regs[REG_A2] != 0);
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memcpy((uint32_t*)regs[REG_A1], regs, XCPTCONTEXT_SIZE);
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up_copystate((uint32_t*)regs[REG_A1], regs);
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current_regs = (uint32_t*)regs[REG_A2];
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}
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break;
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@ -1,413 +1,413 @@
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/********************************************************************************************
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* arch/mips/src/pic32mx/excptmacros.h
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*
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* Copyright (C) 2011 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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********************************************************************************************/
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#ifndef __ARCH_MIPS_SRC_PIC32MX_EXCPTMACROS_H
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#define __ARCH_MIPS_SRC_PIC32MX_EXCPTMACROS_H
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/********************************************************************************************
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* Included Files
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********************************************************************************************/
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#include <nuttx/config.h>
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#include <arch/irq.h>
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#include <arch/pic32mx/cp0.h>
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#ifdef __ASSEMBLY__
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/********************************************************************************************
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* Pre-Processor Definitions
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********************************************************************************************/
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/********************************************************************************************
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* Global Symbols
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********************************************************************************************/
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#if CONFIG_ARCH_INTERRUPTSTACK > 3
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.global g_intstackbase
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.global g_nestlevel
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#endif
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/********************************************************************************************
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* Assembly Language Macros
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********************************************************************************************/
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/********************************************************************************************
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* General Usage Example:
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*
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* my_exception:
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* EXCPT_PROLOGUE t0 - Save registers on stack, enable nested interrupts
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* move a0, sp - Pass register save structure as the parameter 1
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* USE_INTSTACK t0, t1, t2 - Switch to the interrupt stack
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* jal handler - Handle the exception IN=old regs OUT=new regs
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* di - Disable interrupts
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* RESTORE_STACK t0, t1 - Undo the operations of USE_STACK
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* EXCPT_EPILOGUE v0 - Return to the context returned by handler()
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*
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********************************************************************************************/
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/********************************************************************************************
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* Name: EXCPT_PROLOGUE
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*
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* Description:
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* Provides the "prologue" logic that should appear at the beginning of every exception
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* handler.
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*
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* On Entry:
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* sp - Points to the top of the stack
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* tmp - Is a register the can be modified for scratch usage (after it has been saved)
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* k0 and k1 - Since we are in an exception handler, these are available for use
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*
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* At completion:
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* Register state is saved on the stack; All registers are available for usage except sp
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* and k1:
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*
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* - sp points the beginning of the register save area
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* - k1 holds the value of the STATUS register
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*
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* The following registers are modified: k0, k1, sp, a0
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*
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********************************************************************************************/
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.macro EXCPT_PROLOGUE, tmp
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.set noat
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/* Get the SP from the previous shadow set */
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#if 0
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rdpgpr sp, sp
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#endif
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/* "When entering the interrupt handler routine, the interrupt controller must first
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* save the current priority and exception PC counter from Interrupt Priority (IPL)
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* bits (Status<15:10>) and the ErrorEPC register, respectively, on the stack. ..."
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*/
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mfc0 k0, MIPS32_CP0_CAUSE
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mfc0 k1, MIPS32_CP0_EPC
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/* Isolate the pending interrupt level in bits 0-5 of k0 */
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srl k0, k0, CP0_CAUSE_IP_SHIFT
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/* Create the register context stack frame large enough to hold the entire register save
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* array.
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*/
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addiu sp, sp, -XCPTCONTEXT_SIZE
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/* Save the EPC and STATUS in the register context array */
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sw k1, REG_EPC(sp)
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mfc0 k1, MIPS32_CP0_STATUS
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sw k1, REG_STATUS(sp)
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/* Then insert pending interrupt level as the current mask level in the CP0 status
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* register. Also clear bits 1-4 in new value of the status register:
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*
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* Bit 1: Exception Level
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* Bit 2: Error Level
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* Bit 3: (not used in PIC32MX)
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* Bit 4: Operating mode == USER
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*/
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ins k1, \tmp, CP0_STATUS_IPL_SHIFT, 6
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ins k1, zero, 1, 4
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/* And Enable interrupts */
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mtc0 k1, MIPS32_CP0_STATUS
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/* Save floating point registers */
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mfhi k0
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sw k0, REG_MFHI(sp)
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mflo k0
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sw k0, REG_MFLO(sp)
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/* Save general purpose registers */
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/* $1: at_reg, assembler temporary */
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sw $1, REG_AT(sp)
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/* $2-$3 = v0-v1: Return value registers */
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sw v0, REG_V0(sp)
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sw v1, REG_V1(sp)
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/* $4-$7 = a0-a3: Argument registers */
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sw a0, REG_A0(sp)
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sw a1, REG_A1(sp)
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sw a2, REG_A2(sp)
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sw a3, REG_A3(sp)
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/* $8-$15 = t0-t7: Volatile registers */
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sw t0, REG_T0(sp)
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sw t1, REG_T1(sp)
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sw t2, REG_T2(sp)
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sw t3, REG_T3(sp)
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sw t4, REG_T4(sp)
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sw t5, REG_T5(sp)
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sw t6, REG_T6(sp)
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sw t7, REG_T7(sp)
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/* $16-$23 = s0-s7: Static registers */
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sw s0, REG_S0(sp)
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sw s1, REG_S1(sp)
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sw s2, REG_S2(sp)
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sw s3, REG_S3(sp)
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sw s4, REG_S4(sp)
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sw s5, REG_S5(sp)
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sw s6, REG_S6(sp)
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sw s7, REG_S7(sp)
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/* $24-25 = t8-t9: More Volatile registers */
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sw t8, REG_T8(sp)
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sw t9, REG_T9(sp)
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/* $26-$27 = ko-k1: Reserved for use in exeption handers. These do not need to be
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* saved.
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*
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* $28 = gp: Only needs to be saved under conditions where there are multiple, per-
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* thread values for the GP.
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*/
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#ifdef MIPS32_SAVE_GP
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sw gp, REG_GP(sp)
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#endif
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/* $30 = either s8 or fp: Depends if a frame pointer is used or not */
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sw s8, REG_S8(sp)
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/* $31 = ra: Return address */
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sw ra, REG_RA(sp)
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/* $29 = sp: The value of the stack pointer on return from the exception. a0 is
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* used as a temporary
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*/
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addiu \tmp, sp, XCPTCONTEXT_SIZE
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sw \tmp, REG_SP(sp)
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.endm
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/********************************************************************************************
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* Name: EXCPT_EPILOGUE
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*
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* Description:
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* Provides the "epilogue" logic that should appear at the end of every exception handler.
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*
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* On input:
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* regs - points to the register save structure. NOTE: This *may not* be an address
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* lying in a stack! It might be an address in a TCB!
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* Interrupts are disabled (via 'di')
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*
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* On completion:
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* All registers restored
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* eret is executed to return from the exception
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*
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********************************************************************************************/
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.macro EXCPT_EPILOGUE, regs
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.set noat
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/* Since interrupts are disabled via di can now use k0 and k1 again. Use k1 as the
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* pointer to the register save array.
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*/
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move k1, \regs
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/* Restore the floating point register state */
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lw k0, REG_MFLO(k1)
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mtlo k0
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lw k0, REG_MFHI(k1)
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mthi k0
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/* Restore general purpose registers */
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/* $1: at_reg, assembler temporary */
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lw $1, REG_AT(k1)
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/* $2-$3 = v0-v1: Return value registers */
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lw v0, REG_V0(k1)
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lw v1, REG_V1(k1)
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/* $4-$7 = a0-a3: Argument registers */
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lw a0, REG_A0(k1)
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lw a1, REG_A1(k1)
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lw a2, REG_A2(k1)
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lw a3, REG_A3(k1)
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/* $8-$15 = t0-t7: Volatile registers */
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lw t0, REG_T0(k1)
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lw t1, REG_T1(k1)
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lw t2, REG_T2(k1)
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lw t3, REG_T3(k1)
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lw t4, REG_T4(k1)
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lw t5, REG_T5(k1)
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lw t6, REG_T6(k1)
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lw t7, REG_T7(k1)
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/* $16-$23 = s0-s7: Static registers */
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lw s0, REG_S0(k1)
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lw s1, REG_S1(k1)
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lw s2, REG_S2(k1)
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lw s3, REG_S3(k1)
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lw s4, REG_S4(k1)
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lw s5, REG_S5(k1)
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lw s6, REG_S6(k1)
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lw s7, REG_S7(k1)
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/* $24-25 = t8-t9: More Volatile registers */
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lw t8, REG_T8(k1)
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lw t9, REG_T9(k1)
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/* $26-$27 = ko-k1: Reserved for use in exeption handers. These do not need to be
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* saved.
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*
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* $28 = gp: Only needs to be saved under conditions where there are multiple, per-
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* thread values for the GP.
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*/
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#ifdef MIPS32_SAVE_GP
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lw gp, REG_GP(k1)
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#endif
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/* $30 = either s8 or fp: Depends if a frame pointer is used or not */
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lw s8, REG_S8(k1)
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/* $31 = ra: Return address */
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lw ra, REG_RA(k1)
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/* Finally, restore CP status and the EPC */
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lw k0, REG_STATUS(k1)
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lw k1, REG_EPC(k1)
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mtc0 k0, MIPS32_CP0_STATUS
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ehb
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mtc0 k1, MIPS32_CP0_EPC
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eret
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nop
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.endm
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/********************************************************************************************
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* Name: USE_INTSTACK
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*
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* Description:
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* Switch to the interrupt stack (if enabled in the configuration).
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*
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* On Entry:
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* sp - Current value of the user stack pointer
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* tmp1, tmp2, and tmp3 are registers that can be used temporarily.
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* All interrupts should still be disabled.
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*
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* At completion:
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* If the nesting level is 0, then (1) the user stack pointer is saved at the base of the
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* interrupt stack and sp points to the interrupt stack.
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* The values of tmp1, tmp2, tmp3, and sp have been altered
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*
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********************************************************************************************/
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.macro USE_INTSTACK, tmp1, tmp2, tmp3
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#if CONFIG_ARCH_INTERRUPTSTACK > 3
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/* Check the nesting level. If there are no nested interrupts, then we can
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* claim the interrupt stack.
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*/
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la \tmp1, g_nestlevel
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lw \tmp2, (\tmp1)
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bne 1f
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nop
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/* Use the interrupt stack, pushing the user stack pointer onto the interrupt
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* stack first.
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*/
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la \tmp3, g_intstackbase
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lw \tmp, (\tmp3)
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sw sp, (\tmp3)
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move sp, \tmp3
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1:
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/* Increment the interrupt nesting level */
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addiu \tmp2, \tmp2, 1
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sw \tmp2, 0(\tmp1)
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#endif
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.endm
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/********************************************************************************************
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* Name: RESTORE_STACK
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*
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* Description:
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* Restore the user stack. Not really.. actually only decrements the nesting level. We
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* always get the new stack pointer for the register save array.
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*
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* On Entry:
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* tmp1 and tmp2 are registers that can be used temporarily.
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* All interrupts must be disabled.
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*
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* At completion:
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* Current nesting level is decremented
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* The values of tmp1 and tmp2 have been altered
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*
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********************************************************************************************/
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.macro RESTORE_STACK, tmp1, tmp2
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#if CONFIG_ARCH_INTERRUPTSTACK > 3
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/* Decrement the nesting level */
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la \tmp1, g_nestlevel
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lw \tmp2, (\tmp1)
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addiu \tmp2, \tmp2, -1
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sw \tmp2, 0(\tmp1)
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#endif
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.endm
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_MIPS_SRC_PIC32MX_EXCPTMACROS_H */
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/********************************************************************************************
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* arch/mips/src/pic32mx/excptmacros.h
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*
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* Copyright (C) 2011 Gregory Nutt. All rights reserved.
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||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
********************************************************************************************/
|
||||
|
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#ifndef __ARCH_MIPS_SRC_PIC32MX_EXCPTMACROS_H
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#define __ARCH_MIPS_SRC_PIC32MX_EXCPTMACROS_H
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|
||||
/********************************************************************************************
|
||||
* Included Files
|
||||
********************************************************************************************/
|
||||
|
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#include <nuttx/config.h>
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#include <arch/irq.h>
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#include <arch/pic32mx/cp0.h>
|
||||
|
||||
#ifdef __ASSEMBLY__
|
||||
|
||||
/********************************************************************************************
|
||||
* Pre-Processor Definitions
|
||||
********************************************************************************************/
|
||||
|
||||
/********************************************************************************************
|
||||
* Global Symbols
|
||||
********************************************************************************************/
|
||||
|
||||
#if CONFIG_ARCH_INTERRUPTSTACK > 3
|
||||
.global g_intstackbase
|
||||
.global g_nestlevel
|
||||
#endif
|
||||
|
||||
/********************************************************************************************
|
||||
* Assembly Language Macros
|
||||
********************************************************************************************/
|
||||
|
||||
/********************************************************************************************
|
||||
* General Usage Example:
|
||||
*
|
||||
* my_exception:
|
||||
* EXCPT_PROLOGUE t0 - Save registers on stack, enable nested interrupts
|
||||
* move a0, sp - Pass register save structure as the parameter 1
|
||||
* USE_INTSTACK t0, t1, t2 - Switch to the interrupt stack
|
||||
* jal handler - Handle the exception IN=old regs OUT=new regs
|
||||
* di - Disable interrupts
|
||||
* RESTORE_STACK t0, t1 - Undo the operations of USE_STACK
|
||||
* EXCPT_EPILOGUE v0 - Return to the context returned by handler()
|
||||
*
|
||||
********************************************************************************************/
|
||||
/********************************************************************************************
|
||||
* Name: EXCPT_PROLOGUE
|
||||
*
|
||||
* Description:
|
||||
* Provides the "prologue" logic that should appear at the beginning of every exception
|
||||
* handler.
|
||||
*
|
||||
* On Entry:
|
||||
* sp - Points to the top of the stack
|
||||
* tmp - Is a register the can be modified for scratch usage (after it has been saved)
|
||||
* k0 and k1 - Since we are in an exception handler, these are available for use
|
||||
*
|
||||
* At completion:
|
||||
* Register state is saved on the stack; All registers are available for usage except sp
|
||||
* and k1:
|
||||
*
|
||||
* - sp points the beginning of the register save area
|
||||
* - k1 holds the value of the STATUS register
|
||||
*
|
||||
* The following registers are modified: k0, k1, sp, a0
|
||||
*
|
||||
********************************************************************************************/
|
||||
|
||||
.macro EXCPT_PROLOGUE, tmp
|
||||
.set noat
|
||||
|
||||
/* Get the SP from the previous shadow set */
|
||||
|
||||
#if 0
|
||||
rdpgpr sp, sp
|
||||
#endif
|
||||
|
||||
/* "When entering the interrupt handler routine, the interrupt controller must first
|
||||
* save the current priority and exception PC counter from Interrupt Priority (IPL)
|
||||
* bits (Status<15:10>) and the ErrorEPC register, respectively, on the stack. ..."
|
||||
*/
|
||||
|
||||
mfc0 k0, MIPS32_CP0_CAUSE
|
||||
mfc0 k1, MIPS32_CP0_EPC
|
||||
|
||||
/* Isolate the pending interrupt level in bits 0-5 of k0 */
|
||||
|
||||
srl k0, k0, CP0_CAUSE_IP_SHIFT
|
||||
|
||||
/* Create the register context stack frame large enough to hold the entire register save
|
||||
* array.
|
||||
*/
|
||||
|
||||
addiu sp, sp, -XCPTCONTEXT_SIZE
|
||||
|
||||
/* Save the EPC and STATUS in the register context array */
|
||||
|
||||
sw k1, REG_EPC(sp)
|
||||
mfc0 k1, MIPS32_CP0_STATUS
|
||||
sw k1, REG_STATUS(sp)
|
||||
|
||||
/* Then insert pending interrupt level as the current mask level in the CP0 status
|
||||
* register. Also clear bits 1-4 in new value of the status register:
|
||||
*
|
||||
* Bit 1: Exception Level
|
||||
* Bit 2: Error Level
|
||||
* Bit 3: (not used in PIC32MX)
|
||||
* Bit 4: Operating mode == USER
|
||||
*/
|
||||
|
||||
ins k1, \tmp, CP0_STATUS_IPL_SHIFT, 6
|
||||
ins k1, zero, 1, 4
|
||||
|
||||
/* And Enable interrupts */
|
||||
|
||||
mtc0 k1, MIPS32_CP0_STATUS
|
||||
|
||||
/* Save floating point registers */
|
||||
|
||||
mfhi k0
|
||||
sw k0, REG_MFHI(sp)
|
||||
mflo k0
|
||||
sw k0, REG_MFLO(sp)
|
||||
|
||||
/* Save general purpose registers */
|
||||
/* $1: at_reg, assembler temporary */
|
||||
|
||||
sw $1, REG_AT(sp)
|
||||
|
||||
/* $2-$3 = v0-v1: Return value registers */
|
||||
|
||||
sw v0, REG_V0(sp)
|
||||
sw v1, REG_V1(sp)
|
||||
|
||||
/* $4-$7 = a0-a3: Argument registers */
|
||||
|
||||
sw a0, REG_A0(sp)
|
||||
sw a1, REG_A1(sp)
|
||||
sw a2, REG_A2(sp)
|
||||
sw a3, REG_A3(sp)
|
||||
|
||||
/* $8-$15 = t0-t7: Volatile registers */
|
||||
|
||||
sw t0, REG_T0(sp)
|
||||
sw t1, REG_T1(sp)
|
||||
sw t2, REG_T2(sp)
|
||||
sw t3, REG_T3(sp)
|
||||
sw t4, REG_T4(sp)
|
||||
sw t5, REG_T5(sp)
|
||||
sw t6, REG_T6(sp)
|
||||
sw t7, REG_T7(sp)
|
||||
|
||||
/* $16-$23 = s0-s7: Static registers */
|
||||
|
||||
sw s0, REG_S0(sp)
|
||||
sw s1, REG_S1(sp)
|
||||
sw s2, REG_S2(sp)
|
||||
sw s3, REG_S3(sp)
|
||||
sw s4, REG_S4(sp)
|
||||
sw s5, REG_S5(sp)
|
||||
sw s6, REG_S6(sp)
|
||||
sw s7, REG_S7(sp)
|
||||
|
||||
/* $24-25 = t8-t9: More Volatile registers */
|
||||
|
||||
sw t8, REG_T8(sp)
|
||||
sw t9, REG_T9(sp)
|
||||
|
||||
/* $26-$27 = ko-k1: Reserved for use in exeption handers. These do not need to be
|
||||
* saved.
|
||||
*
|
||||
* $28 = gp: Only needs to be saved under conditions where there are multiple, per-
|
||||
* thread values for the GP.
|
||||
*/
|
||||
|
||||
#ifdef MIPS32_SAVE_GP
|
||||
sw gp, REG_GP(sp)
|
||||
#endif
|
||||
|
||||
/* $30 = either s8 or fp: Depends if a frame pointer is used or not */
|
||||
|
||||
sw s8, REG_S8(sp)
|
||||
|
||||
/* $31 = ra: Return address */
|
||||
|
||||
sw ra, REG_RA(sp)
|
||||
|
||||
/* $29 = sp: The value of the stack pointer on return from the exception. a0 is
|
||||
* used as a temporary
|
||||
*/
|
||||
|
||||
addiu \tmp, sp, XCPTCONTEXT_SIZE
|
||||
sw \tmp, REG_SP(sp)
|
||||
.endm
|
||||
|
||||
/********************************************************************************************
|
||||
* Name: EXCPT_EPILOGUE
|
||||
*
|
||||
* Description:
|
||||
* Provides the "epilogue" logic that should appear at the end of every exception handler.
|
||||
*
|
||||
* On input:
|
||||
* regs - points to the register save structure. NOTE: This *may not* be an address
|
||||
* lying in a stack! It might be an address in a TCB!
|
||||
* Interrupts are disabled (via 'di')
|
||||
*
|
||||
* On completion:
|
||||
* All registers restored
|
||||
* eret is executed to return from the exception
|
||||
*
|
||||
********************************************************************************************/
|
||||
|
||||
.macro EXCPT_EPILOGUE, regs
|
||||
.set noat
|
||||
|
||||
/* Since interrupts are disabled via di can now use k0 and k1 again. Use k1 as the
|
||||
* pointer to the register save array.
|
||||
*/
|
||||
|
||||
move k1, \regs
|
||||
|
||||
/* Restore the floating point register state */
|
||||
|
||||
lw k0, REG_MFLO(k1)
|
||||
mtlo k0
|
||||
lw k0, REG_MFHI(k1)
|
||||
mthi k0
|
||||
|
||||
/* Restore general purpose registers */
|
||||
/* $1: at_reg, assembler temporary */
|
||||
|
||||
lw $1, REG_AT(k1)
|
||||
|
||||
/* $2-$3 = v0-v1: Return value registers */
|
||||
|
||||
lw v0, REG_V0(k1)
|
||||
lw v1, REG_V1(k1)
|
||||
|
||||
/* $4-$7 = a0-a3: Argument registers */
|
||||
|
||||
lw a0, REG_A0(k1)
|
||||
lw a1, REG_A1(k1)
|
||||
lw a2, REG_A2(k1)
|
||||
lw a3, REG_A3(k1)
|
||||
|
||||
/* $8-$15 = t0-t7: Volatile registers */
|
||||
|
||||
lw t0, REG_T0(k1)
|
||||
lw t1, REG_T1(k1)
|
||||
lw t2, REG_T2(k1)
|
||||
lw t3, REG_T3(k1)
|
||||
lw t4, REG_T4(k1)
|
||||
lw t5, REG_T5(k1)
|
||||
lw t6, REG_T6(k1)
|
||||
lw t7, REG_T7(k1)
|
||||
|
||||
/* $16-$23 = s0-s7: Static registers */
|
||||
|
||||
lw s0, REG_S0(k1)
|
||||
lw s1, REG_S1(k1)
|
||||
lw s2, REG_S2(k1)
|
||||
lw s3, REG_S3(k1)
|
||||
lw s4, REG_S4(k1)
|
||||
lw s5, REG_S5(k1)
|
||||
lw s6, REG_S6(k1)
|
||||
lw s7, REG_S7(k1)
|
||||
|
||||
/* $24-25 = t8-t9: More Volatile registers */
|
||||
|
||||
lw t8, REG_T8(k1)
|
||||
lw t9, REG_T9(k1)
|
||||
|
||||
/* $26-$27 = ko-k1: Reserved for use in exeption handers. These do not need to be
|
||||
* saved.
|
||||
*
|
||||
* $28 = gp: Only needs to be saved under conditions where there are multiple, per-
|
||||
* thread values for the GP.
|
||||
*/
|
||||
|
||||
#ifdef MIPS32_SAVE_GP
|
||||
lw gp, REG_GP(k1)
|
||||
#endif
|
||||
|
||||
/* $30 = either s8 or fp: Depends if a frame pointer is used or not */
|
||||
|
||||
lw s8, REG_S8(k1)
|
||||
|
||||
/* $31 = ra: Return address */
|
||||
|
||||
lw ra, REG_RA(k1)
|
||||
|
||||
/* Finally, restore CP status and the EPC */
|
||||
|
||||
lw k0, REG_STATUS(k1)
|
||||
lw k1, REG_EPC(k1)
|
||||
mtc0 k0, MIPS32_CP0_STATUS
|
||||
ehb
|
||||
mtc0 k1, MIPS32_CP0_EPC
|
||||
eret
|
||||
nop
|
||||
.endm
|
||||
|
||||
/********************************************************************************************
|
||||
* Name: USE_INTSTACK
|
||||
*
|
||||
* Description:
|
||||
* Switch to the interrupt stack (if enabled in the configuration).
|
||||
*
|
||||
* On Entry:
|
||||
* sp - Current value of the user stack pointer
|
||||
* tmp1, tmp2, and tmp3 are registers that can be used temporarily.
|
||||
* All interrupts should still be disabled.
|
||||
*
|
||||
* At completion:
|
||||
* If the nesting level is 0, then (1) the user stack pointer is saved at the base of the
|
||||
* interrupt stack and sp points to the interrupt stack.
|
||||
* The values of tmp1, tmp2, tmp3, and sp have been altered
|
||||
*
|
||||
********************************************************************************************/
|
||||
|
||||
.macro USE_INTSTACK, tmp1, tmp2, tmp3
|
||||
#if CONFIG_ARCH_INTERRUPTSTACK > 3
|
||||
|
||||
/* Check the nesting level. If there are no nested interrupts, then we can
|
||||
* claim the interrupt stack.
|
||||
*/
|
||||
|
||||
la \tmp1, g_nestlevel
|
||||
lw \tmp2, (\tmp1)
|
||||
bne 1f
|
||||
nop
|
||||
|
||||
/* Use the interrupt stack, pushing the user stack pointer onto the interrupt
|
||||
* stack first.
|
||||
*/
|
||||
|
||||
la \tmp3, g_intstackbase
|
||||
lw \tmp, (\tmp3)
|
||||
sw sp, (\tmp3)
|
||||
move sp, \tmp3
|
||||
1:
|
||||
/* Increment the interrupt nesting level */
|
||||
|
||||
addiu \tmp2, \tmp2, 1
|
||||
sw \tmp2, 0(\tmp1)
|
||||
#endif
|
||||
.endm
|
||||
|
||||
/********************************************************************************************
|
||||
* Name: RESTORE_STACK
|
||||
*
|
||||
* Description:
|
||||
* Restore the user stack. Not really.. actually only decrements the nesting level. We
|
||||
* always get the new stack pointer for the register save array.
|
||||
*
|
||||
* On Entry:
|
||||
* tmp1 and tmp2 are registers that can be used temporarily.
|
||||
* All interrupts must be disabled.
|
||||
*
|
||||
* At completion:
|
||||
* Current nesting level is decremented
|
||||
* The values of tmp1 and tmp2 have been altered
|
||||
*
|
||||
********************************************************************************************/
|
||||
|
||||
.macro RESTORE_STACK, tmp1, tmp2
|
||||
#if CONFIG_ARCH_INTERRUPTSTACK > 3
|
||||
|
||||
/* Decrement the nesting level */
|
||||
|
||||
la \tmp1, g_nestlevel
|
||||
lw \tmp2, (\tmp1)
|
||||
addiu \tmp2, \tmp2, -1
|
||||
sw \tmp2, 0(\tmp1)
|
||||
#endif
|
||||
.endm
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_MIPS_SRC_PIC32MX_EXCPTMACROS_H */
|
||||
|
||||
@ -127,21 +127,9 @@ uint32_t *pic32mx_decodeirq(uint32_t *regs)
|
||||
|
||||
irq = ((regval) & INT_INTSTAT_VEC_MASK) >> INT_INTSTAT_VEC_SHIFT;
|
||||
|
||||
/* Disable further interrupts from this source until the driver has
|
||||
* cleared the pending interrupt sources.
|
||||
*/
|
||||
|
||||
up_disable_irq(irq);
|
||||
|
||||
/* Deliver the IRQ */
|
||||
|
||||
irq_dispatch(irq, regs);
|
||||
|
||||
/* Unmask the last interrupt (global interrupt below the current interrupt
|
||||
* level are are still disabled)
|
||||
*/
|
||||
|
||||
up_enable_irq(irq);
|
||||
}
|
||||
|
||||
/* If a context switch occurred while processing the interrupt then
|
||||
|
||||
@ -435,6 +435,7 @@ _bev_handler:
|
||||
USE_INTSTACK t0, t1, t2 /* Switch to the interrupt stack */
|
||||
la t0, pic32mx_dobev /* Call up_dobev(regs) */
|
||||
jalr ra, t0
|
||||
nop
|
||||
di /* Disable interrupts */
|
||||
RESTORE_STACK t0, t1 /* Undo the operations of USE_STACK */
|
||||
EXCPT_EPILOGUE v0 /* Return to the context returned by up_dobev() */
|
||||
@ -457,6 +458,7 @@ _int_handler:
|
||||
USE_INTSTACK t0, t1, t2 /* Switch to the interrupt stack */
|
||||
la t0, pic32mx_decodeirq /* Call pic32mx_decodeirq(regs) */
|
||||
jalr ra, t0
|
||||
nop
|
||||
di /* Disable interrupts */
|
||||
RESTORE_STACK t0, t1 /* Undo the operations of USE_STACK */
|
||||
EXCPT_EPILOGUE v0 /* Return to the context returned by pic32mx_decodeirq() */
|
||||
@ -480,6 +482,7 @@ _nmi_handler:
|
||||
USE_INTSTACK t0, t1, t2 /* Switch to the interrupt stack */
|
||||
la t0, pic32mx_donmi /* Call up_donmi(regs) */
|
||||
jalr ra, t0
|
||||
nop
|
||||
di /* Disable interrupts */
|
||||
RESTORE_STACK t0, t1 /* Undo the operations of USE_STACK */
|
||||
EXCPT_EPILOGUE v0 /* Return to the context returned by pic32mx_donmi() */
|
||||
|
||||
@ -143,12 +143,17 @@ void up_irqinitialize(void)
|
||||
putreg32(INT_INTCON_MVEC, PIC32MX_INT_INTCONCLR);
|
||||
#endif
|
||||
|
||||
/* Initialize GPIO change notifiction handling */
|
||||
/* Initialize GPIO change notification handling */
|
||||
|
||||
#ifdef CONFIG_GPIO_IRQ
|
||||
pic32mx_gpioirqinitialize();
|
||||
#endif
|
||||
|
||||
/* Attach and enable software interrupts */
|
||||
|
||||
irq_attach(PIC32MX_IRQ_CS0, up_swint0);
|
||||
up_enable_irq(PIC32MX_IRQSRC_CS0);
|
||||
|
||||
/* currents_regs is non-NULL only while processing an interrupt */
|
||||
|
||||
current_regs = NULL;
|
||||
@ -194,14 +199,14 @@ void up_disable_irq(int irq)
|
||||
/* Use IEC0 */
|
||||
|
||||
regaddr = PIC32MX_INT_IEC0CLR;
|
||||
bitno -= PIC32MX_IRQSRC0_FIRST;
|
||||
bitno = irq - PIC32MX_IRQSRC0_FIRST;
|
||||
}
|
||||
else if (irq <= PIC32MX_IRQSRC1_LAST)
|
||||
{
|
||||
/* Use IEC1 */
|
||||
|
||||
regaddr = PIC32MX_INT_IEC1CLR;
|
||||
bitno -= PIC32MX_IRQSRC1_FIRST;
|
||||
bitno = irq - PIC32MX_IRQSRC1_FIRST;
|
||||
}
|
||||
#ifdef PIC32MX_IRQSRC2_FIRST
|
||||
else if (irq <= PIC32MX_IRQSRC2_LAST)
|
||||
@ -209,7 +214,7 @@ void up_disable_irq(int irq)
|
||||
/* Use IEC2 */
|
||||
|
||||
regaddr = PIC32MX_INT_IEC2CLR;
|
||||
bitno -= PIC32MX_IRQSRC2_FIRST;
|
||||
bitno = irq - PIC32MX_IRQSRC2_FIRST;
|
||||
}
|
||||
#endif
|
||||
else
|
||||
@ -248,14 +253,14 @@ void up_enable_irq(int irq)
|
||||
/* Use IEC0 */
|
||||
|
||||
regaddr = PIC32MX_INT_IEC0SET;
|
||||
bitno -= PIC32MX_IRQSRC0_FIRST;
|
||||
bitno = irq - PIC32MX_IRQSRC0_FIRST;
|
||||
}
|
||||
else if (irq <= PIC32MX_IRQSRC1_LAST)
|
||||
{
|
||||
/* Use IEC1 */
|
||||
|
||||
regaddr = PIC32MX_INT_IEC1SET;
|
||||
bitno -= PIC32MX_IRQSRC1_FIRST;
|
||||
bitno = irq - PIC32MX_IRQSRC1_FIRST;
|
||||
}
|
||||
#ifdef PIC32MX_IRQSRC2_FIRST
|
||||
else if (irq <= PIC32MX_IRQSRC2_LAST)
|
||||
@ -263,7 +268,7 @@ void up_enable_irq(int irq)
|
||||
/* Use IEC2 */
|
||||
|
||||
regaddr = PIC32MX_INT_IEC2SET;
|
||||
bitno -= PIC32MX_IRQSRC2_FIRST;
|
||||
bitno = irq - PIC32MX_IRQSRC2_FIRST;
|
||||
}
|
||||
#endif
|
||||
else
|
||||
|
||||
Loading…
Reference in New Issue
Block a user