More PIC32 debug updates
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4083 42af7a65-404d-4744-a932-0658087f49c3
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@ -182,6 +182,10 @@ extern void up_dumpstate(void);
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extern uint32_t *up_doirq(int irq, uint32_t *regs);
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extern uint32_t *up_doirq(int irq, uint32_t *regs);
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/* Software interrupt 0 handler */
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extern int up_swint0(int irq, FAR void *context);
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/* Signals */
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/* Signals */
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extern void up_sigdeliver(void);
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extern void up_sigdeliver(void);
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@ -326,7 +326,7 @@ int up_swint0(int irq, FAR void *context)
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case SYS_switch_context:
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case SYS_switch_context:
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{
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{
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DEBUGASSERT(regs[REG_A1] != 0 && regs[REG_A2] != 0);
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DEBUGASSERT(regs[REG_A1] != 0 && regs[REG_A2] != 0);
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memcpy((uint32_t*)regs[REG_A1], regs, XCPTCONTEXT_SIZE);
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up_copystate((uint32_t*)regs[REG_A1], regs);
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current_regs = (uint32_t*)regs[REG_A2];
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current_regs = (uint32_t*)regs[REG_A2];
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}
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}
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break;
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break;
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@ -127,21 +127,9 @@ uint32_t *pic32mx_decodeirq(uint32_t *regs)
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irq = ((regval) & INT_INTSTAT_VEC_MASK) >> INT_INTSTAT_VEC_SHIFT;
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irq = ((regval) & INT_INTSTAT_VEC_MASK) >> INT_INTSTAT_VEC_SHIFT;
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/* Disable further interrupts from this source until the driver has
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* cleared the pending interrupt sources.
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*/
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up_disable_irq(irq);
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/* Deliver the IRQ */
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/* Deliver the IRQ */
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irq_dispatch(irq, regs);
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irq_dispatch(irq, regs);
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/* Unmask the last interrupt (global interrupt below the current interrupt
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* level are are still disabled)
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*/
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up_enable_irq(irq);
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}
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}
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/* If a context switch occurred while processing the interrupt then
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/* If a context switch occurred while processing the interrupt then
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@ -435,6 +435,7 @@ _bev_handler:
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USE_INTSTACK t0, t1, t2 /* Switch to the interrupt stack */
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USE_INTSTACK t0, t1, t2 /* Switch to the interrupt stack */
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la t0, pic32mx_dobev /* Call up_dobev(regs) */
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la t0, pic32mx_dobev /* Call up_dobev(regs) */
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jalr ra, t0
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jalr ra, t0
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nop
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di /* Disable interrupts */
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di /* Disable interrupts */
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RESTORE_STACK t0, t1 /* Undo the operations of USE_STACK */
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RESTORE_STACK t0, t1 /* Undo the operations of USE_STACK */
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EXCPT_EPILOGUE v0 /* Return to the context returned by up_dobev() */
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EXCPT_EPILOGUE v0 /* Return to the context returned by up_dobev() */
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@ -457,6 +458,7 @@ _int_handler:
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USE_INTSTACK t0, t1, t2 /* Switch to the interrupt stack */
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USE_INTSTACK t0, t1, t2 /* Switch to the interrupt stack */
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la t0, pic32mx_decodeirq /* Call pic32mx_decodeirq(regs) */
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la t0, pic32mx_decodeirq /* Call pic32mx_decodeirq(regs) */
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jalr ra, t0
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jalr ra, t0
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nop
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di /* Disable interrupts */
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di /* Disable interrupts */
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RESTORE_STACK t0, t1 /* Undo the operations of USE_STACK */
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RESTORE_STACK t0, t1 /* Undo the operations of USE_STACK */
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EXCPT_EPILOGUE v0 /* Return to the context returned by pic32mx_decodeirq() */
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EXCPT_EPILOGUE v0 /* Return to the context returned by pic32mx_decodeirq() */
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@ -480,6 +482,7 @@ _nmi_handler:
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USE_INTSTACK t0, t1, t2 /* Switch to the interrupt stack */
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USE_INTSTACK t0, t1, t2 /* Switch to the interrupt stack */
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la t0, pic32mx_donmi /* Call up_donmi(regs) */
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la t0, pic32mx_donmi /* Call up_donmi(regs) */
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jalr ra, t0
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jalr ra, t0
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nop
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di /* Disable interrupts */
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di /* Disable interrupts */
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RESTORE_STACK t0, t1 /* Undo the operations of USE_STACK */
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RESTORE_STACK t0, t1 /* Undo the operations of USE_STACK */
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EXCPT_EPILOGUE v0 /* Return to the context returned by pic32mx_donmi() */
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EXCPT_EPILOGUE v0 /* Return to the context returned by pic32mx_donmi() */
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@ -143,12 +143,17 @@ void up_irqinitialize(void)
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putreg32(INT_INTCON_MVEC, PIC32MX_INT_INTCONCLR);
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putreg32(INT_INTCON_MVEC, PIC32MX_INT_INTCONCLR);
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#endif
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#endif
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/* Initialize GPIO change notifiction handling */
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/* Initialize GPIO change notification handling */
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#ifdef CONFIG_GPIO_IRQ
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#ifdef CONFIG_GPIO_IRQ
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pic32mx_gpioirqinitialize();
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pic32mx_gpioirqinitialize();
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#endif
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#endif
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/* Attach and enable software interrupts */
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irq_attach(PIC32MX_IRQ_CS0, up_swint0);
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up_enable_irq(PIC32MX_IRQSRC_CS0);
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/* currents_regs is non-NULL only while processing an interrupt */
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/* currents_regs is non-NULL only while processing an interrupt */
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current_regs = NULL;
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current_regs = NULL;
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@ -194,14 +199,14 @@ void up_disable_irq(int irq)
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/* Use IEC0 */
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/* Use IEC0 */
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regaddr = PIC32MX_INT_IEC0CLR;
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regaddr = PIC32MX_INT_IEC0CLR;
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bitno -= PIC32MX_IRQSRC0_FIRST;
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bitno = irq - PIC32MX_IRQSRC0_FIRST;
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}
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}
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else if (irq <= PIC32MX_IRQSRC1_LAST)
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else if (irq <= PIC32MX_IRQSRC1_LAST)
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{
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{
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/* Use IEC1 */
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/* Use IEC1 */
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regaddr = PIC32MX_INT_IEC1CLR;
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regaddr = PIC32MX_INT_IEC1CLR;
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bitno -= PIC32MX_IRQSRC1_FIRST;
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bitno = irq - PIC32MX_IRQSRC1_FIRST;
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}
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}
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#ifdef PIC32MX_IRQSRC2_FIRST
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#ifdef PIC32MX_IRQSRC2_FIRST
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else if (irq <= PIC32MX_IRQSRC2_LAST)
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else if (irq <= PIC32MX_IRQSRC2_LAST)
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@ -209,7 +214,7 @@ void up_disable_irq(int irq)
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/* Use IEC2 */
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/* Use IEC2 */
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regaddr = PIC32MX_INT_IEC2CLR;
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regaddr = PIC32MX_INT_IEC2CLR;
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bitno -= PIC32MX_IRQSRC2_FIRST;
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bitno = irq - PIC32MX_IRQSRC2_FIRST;
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}
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}
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#endif
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#endif
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else
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else
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@ -248,14 +253,14 @@ void up_enable_irq(int irq)
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/* Use IEC0 */
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/* Use IEC0 */
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regaddr = PIC32MX_INT_IEC0SET;
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regaddr = PIC32MX_INT_IEC0SET;
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bitno -= PIC32MX_IRQSRC0_FIRST;
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bitno = irq - PIC32MX_IRQSRC0_FIRST;
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}
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}
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else if (irq <= PIC32MX_IRQSRC1_LAST)
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else if (irq <= PIC32MX_IRQSRC1_LAST)
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{
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{
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/* Use IEC1 */
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/* Use IEC1 */
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regaddr = PIC32MX_INT_IEC1SET;
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regaddr = PIC32MX_INT_IEC1SET;
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bitno -= PIC32MX_IRQSRC1_FIRST;
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bitno = irq - PIC32MX_IRQSRC1_FIRST;
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}
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}
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#ifdef PIC32MX_IRQSRC2_FIRST
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#ifdef PIC32MX_IRQSRC2_FIRST
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else if (irq <= PIC32MX_IRQSRC2_LAST)
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else if (irq <= PIC32MX_IRQSRC2_LAST)
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@ -263,7 +268,7 @@ void up_enable_irq(int irq)
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/* Use IEC2 */
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/* Use IEC2 */
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regaddr = PIC32MX_INT_IEC2SET;
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regaddr = PIC32MX_INT_IEC2SET;
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bitno -= PIC32MX_IRQSRC2_FIRST;
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bitno = irq - PIC32MX_IRQSRC2_FIRST;
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}
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}
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#endif
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#endif
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else
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else
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