From 02978c797a876ca1e56e0b684ab8040e53689f76 Mon Sep 17 00:00:00 2001
From: Gregory Nutt <gnutt@nuttx.org>
Date: Fri, 1 Apr 2016 14:52:17 -0600
Subject: [PATCH] i.MX6: Straighten up some glock gating

---
 arch/arm/src/imx6/imx_clockconfig.c |  9 ---------
 arch/arm/src/imx6/imx_lowputc.c     |  9 +++++----
 arch/arm/src/imx6/imx_timerisr.c    | 13 +++++++++++++
 3 files changed, 18 insertions(+), 13 deletions(-)

diff --git a/arch/arm/src/imx6/imx_clockconfig.c b/arch/arm/src/imx6/imx_clockconfig.c
index 855da584c3..68613e4c07 100644
--- a/arch/arm/src/imx6/imx_clockconfig.c
+++ b/arch/arm/src/imx6/imx_clockconfig.c
@@ -60,8 +60,6 @@
 
 void imx_clockconfig(void)
 {
-  uint32_t regval;
-
   /* Don't change the current basic clock configuration if we are running
    * from SDRAM.  In this case, some bootloader logic has already configured
    * clocking and SDRAM.  We are pretty much committed to using things the
@@ -77,11 +75,4 @@ void imx_clockconfig(void)
 #ifndef CONFIG_IMX6_BOOT_SDRAM
 #  warning Missing logic
 #endif
-
-  /* Make certain that the ipg_clk is enabled */
-
-  regval  = getreg32(IMX_CCM_CCGR5);
-  regval &= ~(CCM_CCGR5_CG12_MASK);
-  regval |= CCM_CCGR5_CG12(CCM_CCGR_ALLMODES);
-  putreg32(regval, IMX_CCM_CCGR5);
 }
diff --git a/arch/arm/src/imx6/imx_lowputc.c b/arch/arm/src/imx6/imx_lowputc.c
index 690a77f50e..a6387e7321 100644
--- a/arch/arm/src/imx6/imx_lowputc.c
+++ b/arch/arm/src/imx6/imx_lowputc.c
@@ -165,14 +165,15 @@ void imx_lowsetup(void)
 #ifdef IMX_HAVE_UART
   uint32_t regval;
 
-  /* Make certain that the ipg_perclk is enabled.  The ipg_clk should already
-   * have been enabled.  Here we set BOTH the ipg_clk and ipg_perclk so that
-   * clocking is on in all modes (except STOP).
+  /* Make certain that the ipg_clock and ipg_perclk are enabled for the UART
+   * modules.  Here we set BOTH the ipg_clk and ipg_perclk so that clocking
+   * is on in all modes (except STOP).
    */
 
   regval  = getreg32(IMX_CCM_CCGR5);
   regval &= ~(CCM_CCGR5_CG12_MASK | CCM_CCGR5_CG13_MASK);
-  regval |= (CCM_CCGR5_CG12(CCM_CCGR_ALLMODES) | CCM_CCGR5_CG13(CCM_CCGR_ALLMODES));
+  regval |= (CCM_CCGR5_CG12(CCM_CCGR_ALLMODES) |
+             CCM_CCGR5_CG13(CCM_CCGR_ALLMODES));
   putreg32(regval, IMX_CCM_CCGR5);
 
 #ifdef CONFIG_IMX6_UART1
diff --git a/arch/arm/src/imx6/imx_timerisr.c b/arch/arm/src/imx6/imx_timerisr.c
index 6d46447a12..50d405973f 100644
--- a/arch/arm/src/imx6/imx_timerisr.c
+++ b/arch/arm/src/imx6/imx_timerisr.c
@@ -46,6 +46,7 @@
 #include <arch/irq.h>
 
 #include "up_arch.h"
+#include "chip/imx_ccm.h"
 #include "chip/imx_gpt.h"
 
 /****************************************************************************
@@ -143,12 +144,24 @@ int up_timerisr(int irq, uint32_t *regs)
 
 void up_timer_initialize(void)
 {
+  uint32_t regval;
   uint32_t cr;
 
   /* Disable GPT interrupts at the GIC */
 
   up_disable_irq(IMX_IRQ_GPT);
 
+  /* Make certain that the ipg_clock and ipg_clk_highfreq are enabled for
+   * the GPT module.  Here we set BOTH the ipg_clk and ipg_clk_highfreq so
+   * that clocking is on in all modes (except STOP).
+   */
+
+  regval  = getreg32(IMX_CCM_CCGR1);
+  regval &= ~(CCM_CCGR1_CG10_MASK | CCM_CCGR1_CG11_MASK);
+  regval |= (CCM_CCGR1_CG10(CCM_CCGR_ALLMODES) |
+             CCM_CCGR1_CG11(CCM_CCGR_ALLMODES));
+  putreg32(regval, IMX_CCM_CCGR1);
+
   /* Disable GPT by setting EN=0 in GPT_CR register */
 
   cr = getreg32(IMX_GPT_CR);