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i.MX6: Straighten up some glock gating

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This commit is contained in:
Gregory Nutt 2016-04-01 14:52:17 -06:00
parent 84b399136e
commit 02978c797a
3 changed files with 18 additions and 13 deletions
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9
arch/arm/src/imx6/imx_clockconfig.c
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@ -60,8 +60,6 @@
void imx_clockconfig(void) void imx_clockconfig(void)
{ {
uint32_t regval;
/* Don't change the current basic clock configuration if we are running /* Don't change the current basic clock configuration if we are running
* from SDRAM. In this case, some bootloader logic has already configured * from SDRAM. In this case, some bootloader logic has already configured
* clocking and SDRAM. We are pretty much committed to using things the * clocking and SDRAM. We are pretty much committed to using things the
@ -77,11 +75,4 @@ void imx_clockconfig(void)
#ifndef CONFIG_IMX6_BOOT_SDRAM #ifndef CONFIG_IMX6_BOOT_SDRAM
# warning Missing logic # warning Missing logic
#endif #endif
/* Make certain that the ipg_clk is enabled */
regval = getreg32(IMX_CCM_CCGR5);
regval &= ~(CCM_CCGR5_CG12_MASK);
regval |= CCM_CCGR5_CG12(CCM_CCGR_ALLMODES);
putreg32(regval, IMX_CCM_CCGR5);
} }

9
arch/arm/src/imx6/imx_lowputc.c
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@ -165,14 +165,15 @@ void imx_lowsetup(void)
#ifdef IMX_HAVE_UART #ifdef IMX_HAVE_UART
uint32_t regval; uint32_t regval;
/* Make certain that the ipg_perclk is enabled. The ipg_clk should already /* Make certain that the ipg_clock and ipg_perclk are enabled for the UART
* have been enabled. Here we set BOTH the ipg_clk and ipg_perclk so that * modules. Here we set BOTH the ipg_clk and ipg_perclk so that clocking
* clocking is on in all modes (except STOP). * is on in all modes (except STOP).
*/ */
regval = getreg32(IMX_CCM_CCGR5); regval = getreg32(IMX_CCM_CCGR5);
regval &= ~(CCM_CCGR5_CG12_MASK | CCM_CCGR5_CG13_MASK); regval &= ~(CCM_CCGR5_CG12_MASK | CCM_CCGR5_CG13_MASK);
regval |= (CCM_CCGR5_CG12(CCM_CCGR_ALLMODES) | CCM_CCGR5_CG13(CCM_CCGR_ALLMODES)); regval |= (CCM_CCGR5_CG12(CCM_CCGR_ALLMODES) |
CCM_CCGR5_CG13(CCM_CCGR_ALLMODES));
putreg32(regval, IMX_CCM_CCGR5); putreg32(regval, IMX_CCM_CCGR5);
#ifdef CONFIG_IMX6_UART1 #ifdef CONFIG_IMX6_UART1

13
arch/arm/src/imx6/imx_timerisr.c
View File

@ -46,6 +46,7 @@
#include <arch/irq.h> #include <arch/irq.h>
#include "up_arch.h" #include "up_arch.h"
#include "chip/imx_ccm.h"
#include "chip/imx_gpt.h" #include "chip/imx_gpt.h"
/**************************************************************************** /****************************************************************************
@ -143,12 +144,24 @@ int up_timerisr(int irq, uint32_t *regs)
void up_timer_initialize(void) void up_timer_initialize(void)
{ {
uint32_t regval;
uint32_t cr; uint32_t cr;
/* Disable GPT interrupts at the GIC */ /* Disable GPT interrupts at the GIC */
up_disable_irq(IMX_IRQ_GPT); up_disable_irq(IMX_IRQ_GPT);
/* Make certain that the ipg_clock and ipg_clk_highfreq are enabled for
* the GPT module. Here we set BOTH the ipg_clk and ipg_clk_highfreq so
* that clocking is on in all modes (except STOP).
*/
regval = getreg32(IMX_CCM_CCGR1);
regval &= ~(CCM_CCGR1_CG10_MASK | CCM_CCGR1_CG11_MASK);
regval |= (CCM_CCGR1_CG10(CCM_CCGR_ALLMODES) |
CCM_CCGR1_CG11(CCM_CCGR_ALLMODES));
putreg32(regval, IMX_CCM_CCGR1);
/* Disable GPT by setting EN=0 in GPT_CR register */ /* Disable GPT by setting EN=0 in GPT_CR register */
cr = getreg32(IMX_GPT_CR); cr = getreg32(IMX_GPT_CR);