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arch/esp32: Simplify the interrupt allocation process.

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Allocating and attaching interrupts were both exported outside, however
these two move hand in hand and we don't have to expose these details.
Also, the parameters passed are saved and will be used to retrieve
information about the interrupt and the attached peripheral.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
This commit is contained in:
Abdelatif Guettouche 2021-08-17 16:35:00 +02:00 committed by Masayuki Ishikawa
parent eefe7ebe5f
commit 02c17c3169
12 changed files with 215 additions and 290 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

240
arch/xtensa/src/esp32/esp32_cpuint.c
View File

@ -228,7 +228,6 @@ static inline void xtensa_disable_all(void)
static int esp32_getcpuint(uint32_t intmask)
{
irqstate_t flags;
uint32_t *freeints;
uint32_t bitmask;
uint32_t intset;
@ -240,8 +239,6 @@ static int esp32_getcpuint(uint32_t intmask)
* available.
*/
flags = enter_critical_section();
cpu = up_cpu_index();
#ifdef CONFIG_SMP
if (cpu != 0)
@ -294,10 +291,96 @@ static int esp32_getcpuint(uint32_t intmask)
xtensa_disable_cpuint(&g_intenable[cpu], (1ul << ret));
}
leave_critical_section(flags);
return ret;
}
/****************************************************************************
* Name: esp32_alloc_cpuint
*
* Description:
* Allocate a level CPU interrupt
*
* Input Parameters:
* priority - Priority of the CPU interrupt (1-5)
* type - Interrupt type (level or edge).
*
* Returned Value:
* On success, the allocated CPU interrupt number is returned.
* A negated errno is returned on failure. The only possible failure
* is that all CPU interrupts of the requested type have already been
* allocated.
*
****************************************************************************/
static int esp32_alloc_cpuint(int priority, int type)
{
uint32_t mask;
DEBUGASSERT(priority >= ESP32_MIN_PRIORITY &&
priority <= ESP32_MAX_PRIORITY);
DEBUGASSERT(type == ESP32_CPUINT_LEVEL ||
type == ESP32_CPUINT_EDGE);
if (type == ESP32_CPUINT_LEVEL)
{
/* Check if there are any level CPU interrupts available at the
* requested interrupt priority.
*/
mask = g_priority[ESP32_PRIO_INDEX(priority)] & ESP32_CPUINT_LEVELSET;
}
else
{
/* Check if there are any edge CPU interrupts available at the
* requested interrupt priority.
*/
mask = g_priority[ESP32_PRIO_INDEX(priority)] & ESP32_CPUINT_EDGESET;
}
return esp32_getcpuint(mask);
}
/****************************************************************************
* Name: esp32_free_cpuint
*
* Description:
* Free a previously allocated CPU interrupt
*
* Input Parameters:
* The CPU interrupt number to be freed
*
* Returned Value:
* None
*
****************************************************************************/
static void esp32_free_cpuint(int cpuint)
{
uint32_t *freeints;
uint32_t bitmask;
DEBUGASSERT(cpuint >= 0 && cpuint <= ESP32_CPUINT_MAX);
/* Mark the CPU interrupt as available */
bitmask = (1ul << cpuint);
#ifdef CONFIG_SMP
if (up_cpu_index() != 0)
{
freeints = &g_cpu1_freeints;
}
else
#endif
{
freeints = &g_cpu0_freeints;
}
DEBUGASSERT((*freeints & bitmask) == 0);
*freeints |= bitmask;
}
/****************************************************************************
* Public Functions
****************************************************************************/
@ -399,117 +482,50 @@ int esp32_cpuint_initialize(void)
}
/****************************************************************************
* Name: esp32_alloc_cpuint
* Name: esp32_setup_irq
*
* Description:
* Allocate a level CPU interrupt
*
* Input Parameters:
* priority - Priority of the CPU interrupt (1-5)
*
* Returned Value:
* On success, the allocated CPU interrupt number is returned.
* A negated errno is returned on failure. The only possible failure
* is that all CPU interrupts of the requested type have already been
* allocated.
*
****************************************************************************/
int esp32_alloc_cpuint(int priority, int type)
{
uint32_t mask;
DEBUGASSERT(priority >= ESP32_MIN_PRIORITY &&
priority <= ESP32_MAX_PRIORITY);
DEBUGASSERT(type == ESP32_CPUINT_LEVEL ||
type == ESP32_CPUINT_EDGE);
if (type == ESP32_CPUINT_LEVEL)
{
/* Check if there are any level CPU interrupts available at the
* requested interrupt priority.
*/
mask = g_priority[ESP32_PRIO_INDEX(priority)] & ESP32_CPUINT_LEVELSET;
}
else
{
/* Check if there are any edge CPU interrupts available at the
* requested interrupt priority.
*/
mask = g_priority[ESP32_PRIO_INDEX(priority)] & ESP32_CPUINT_EDGESET;
}
return esp32_getcpuint(mask);
}
/****************************************************************************
* Name: esp32_free_cpuint
*
* Description:
* Free a previously allocated CPU interrupt
*
* Input Parameters:
* The CPU interrupt number to be freed
*
* Returned Value:
* None
*
****************************************************************************/
void esp32_free_cpuint(int cpuint)
{
irqstate_t flags;
uint32_t *freeints;
uint32_t bitmask;
DEBUGASSERT(cpuint >= 0 && cpuint <= ESP32_CPUINT_MAX);
/* Mark the CPU interrupt as available */
bitmask = (1ul << cpuint);
flags = enter_critical_section();
#ifdef CONFIG_SMP
if (up_cpu_index() != 0)
{
freeints = &g_cpu1_freeints;
}
else
#endif
{
freeints = &g_cpu0_freeints;
}
DEBUGASSERT((*freeints & bitmask) == 0);
*freeints |= bitmask;
leave_critical_section(flags);
}
/****************************************************************************
* Name: esp32_attach_peripheral
*
* Description:
* Attach a peripheral interrupt to a CPU interrupt.
* This function sets up the IRQ. It allocates a CPU interrupt of the given
* priority and type and attaches it to the given peripheral.
*
* Input Parameters:
* cpu - The CPU to receive the interrupt 0=PRO CPU 1=APP CPU
* periphid - The peripheral number from irq.h to be assigned to
* a CPU interrupt.
* cpuint - The CPU interrupt to receive the peripheral interrupt
* assignment.
* priority - Interrupt's priority (1 - 5).
* type - Interrupt's type (level or edge).
*
* Returned Value:
* None
* The allocated CPU interrupt on success, a negated errno value on
* failure.
*
****************************************************************************/
void esp32_attach_peripheral(int cpu, int periphid, int cpuint)
int esp32_setup_irq(int cpu, int periphid, int priority, int type)
{
irqstate_t irqstate;
uintptr_t regaddr;
uint8_t *intmap;
int irq;
int cpuint;
irqstate = enter_critical_section();
/* Setting up an IRQ includes the following steps:
* 1. Allocate a CPU interrupt.
* 2. Attach that CPU interrup to the peripheral.
* 3. Map the CPU interrupt to the IRQ to ease searching later.
*/
cpuint = esp32_alloc_cpuint(priority, type);
if (cpuint < 0)
{
irqerr("Unable to allocate CPU interrupt for priority=%d and type=%d",
priority, type);
leave_critical_section(irqstate);
return cpuint;
}
irq = ESP32_PERIPH2IRQ(periphid);
@ -531,17 +547,24 @@ void esp32_attach_peripheral(int cpu, int periphid, int cpuint)
}
DEBUGASSERT(intmap[cpuint] == CPUINT_UNASSIGNED);
intmap[cpuint] = periphid + XTENSA_IRQ_FIRSTPERIPH;
esp32_mapirq(irq, cpu, cpuint);
putreg32(cpuint, regaddr);
leave_critical_section(irqstate);
return cpuint;
}
/****************************************************************************
* Name: esp32_detach_peripheral
* Name: esp32_teardown_irq
*
* Description:
* Detach a peripheral interrupt from a CPU interrupt.
* This function undoes the operations done by esp32_setup_irq.
* It detaches a peripheral interrupt from a CPU interrupt and frees the
* CPU interrupt.
*
* Input Parameters:
* cpu - The CPU to receive the interrupt 0=PRO CPU 1=APP CPU
@ -555,12 +578,23 @@ void esp32_attach_peripheral(int cpu, int periphid, int cpuint)
*
****************************************************************************/
void esp32_detach_peripheral(int cpu, int periphid, int cpuint)
void esp32_teardown_irq(int cpu, int periphid, int cpuint)
{
irqstate_t irqstate;
uintptr_t regaddr;
uint8_t *intmap;
int irq;
irqstate = enter_critical_section();
/* Tearing down an IRQ includes the following steps:
* 1. Free the previously allocated CPU interrupt.
* 2. Detach the interrupt from the peripheral.
* 3. Unmap the IRQ from the IRQ-to-cpuint map.
*/
esp32_free_cpuint(cpuint);
irq = ESP32_PERIPH2IRQ(periphid);
DEBUGASSERT(periphid >= 0 && periphid < ESP32_NPERIPHERALS);
@ -584,4 +618,6 @@ void esp32_detach_peripheral(int cpu, int periphid, int cpuint)
esp32_unmapirq(irq);
putreg32(NO_CPUINT, regaddr);
leave_critical_section(irqstate);
}

57
arch/xtensa/src/esp32/esp32_cpuint.h
View File

@ -85,65 +85,34 @@ extern uint32_t g_intenable[1];
int esp32_cpuint_initialize(void);
/****************************************************************************
* Name: esp32_alloc_cpuint
* Name: esp32_setup_irq
*
* Description:
* Allocate a level CPU interrupt
*
* Input Parameters:
* priority - Priority of the CPU interrupt (1-5)
*
* Returned Value:
* On success, the allocated CPU interrupt number is returned.
* A negated errno is returned on failure. The only possible failure
* is that all CPU interrupts of the requested type have already been
* allocated.
*
****************************************************************************/
int esp32_alloc_cpuint(int priority, int type);
/****************************************************************************
* Name: esp32_free_cpuint
*
* Description:
* Free a previoulsy allocated CPU interrupt
*
* Input Parameters:
* cpuint - The CPU interrupt number to be freed
*
* Returned Value:
* None
*
****************************************************************************/
void esp32_free_cpuint(int cpuint);
/****************************************************************************
* Name: esp32_attach_peripheral
*
* Description:
* Attach a peripheral interrupt to a CPU interrupt.
* This function sets up the IRQ. It allocates a CPU interrupt of the given
* priority and type and attaches it to the given peripheral.
*
* Input Parameters:
* cpu - The CPU to receive the interrupt 0=PRO CPU 1=APP CPU
* periphid - The peripheral number from irq.h to be assigned to
* a CPU interrupt.
* cpuint - The CPU interrupt to receive the peripheral interrupt
* assignment.
* priority - Interrupt's priority (1 - 5).
* type - Interrupt's type (level or edge).
*
* Returned Value:
* None
* The allocated CPU interrupt on success, a negated errno value on
* failure.
*
****************************************************************************/
void esp32_attach_peripheral(int cpu, int periphid, int cpuint);
int esp32_setup_irq(int cpu, int periphid, int priority, int type);
/****************************************************************************
* Name: esp32_detach_peripheral
* Name: esp32_teardown_irq
*
* Description:
* Detach a peripheral interrupt from a CPU interrupt.
* This function undoes the operations done by esp32_setup_irq.
* It detaches a peripheral interrupt from a CPU interrupt and frees the
* CPU interrupt.
*
* Input Parameters:
* cpu - The CPU to receive the interrupt 0=PRO CPU 1=APP CPU
@ -157,6 +126,6 @@ void esp32_attach_peripheral(int cpu, int periphid, int cpuint);
*
****************************************************************************/
void esp32_detach_peripheral(int cpu, int periphid, int cpuint);
void esp32_teardown_irq(int cpu, int periphid, int cpuint);
#endif /* __ARCH_XTENSA_SRC_ESP32_ESP32_CPUINT_H */

8
arch/xtensa/src/esp32/esp32_cpustart.c
View File

@ -90,14 +90,10 @@ static inline void xtensa_attach_fromcpu0_interrupt(void)
{
int cpuint;
/* Allocate a level-sensitive, priority 1 CPU interrupt for the UART */
cpuint = esp32_alloc_cpuint(1, ESP32_CPUINT_LEVEL);
DEBUGASSERT(cpuint >= 0);
/* Connect all CPU peripheral source to allocated CPU interrupt */
esp32_attach_peripheral(1, ESP32_PERIPH_CPU_CPU0, cpuint);
cpuint = esp32_setup_irq(1, ESP32_PERIPH_CPU_CPU0, 1, ESP32_CPUINT_LEVEL);
DEBUGASSERT(cpuint >= 0);
/* Attach the inter-CPU interrupt. */

10
arch/xtensa/src/esp32/esp32_emac.c
View File

@ -2185,9 +2185,8 @@ int esp32_emac_init(void)
memset(priv, 0, sizeof(struct esp32_emac_s));
/* Allocate and register interrupt */
priv->cpuint = esp32_alloc_cpuint(1, ESP32_CPUINT_LEVEL);
priv->cpuint = esp32_setup_irq(0, ESP32_PERIPH_EMAC,
1, ESP32_CPUINT_LEVEL);
if (priv->cpuint < 0)
{
nerr("ERROR: Failed alloc interrupt\n");
@ -2196,8 +2195,6 @@ int esp32_emac_init(void)
goto error;
}
esp32_attach_peripheral(0, ESP32_PERIPH_EMAC, priv->cpuint);
ret = irq_attach(ESP32_IRQ_EMAC, emac_interrupt, priv);
if (ret != 0)
{
@ -2239,8 +2236,7 @@ int esp32_emac_init(void)
return 0;
errout_with_attachirq:
esp32_detach_peripheral(0, ESP32_PERIPH_EMAC, priv->cpuint);
esp32_free_cpuint(priv->cpuint);
esp32_teardown_irq(0, ESP32_PERIPH_EMAC, priv->cpuint);
error:
return ret;

13
arch/xtensa/src/esp32/esp32_gpio.c
View File

@ -410,18 +410,13 @@ void esp32_gpioirqinitialize(void)
{
int cpu;
/* Allocate a level-sensitive, priority 1 CPU interrupt */
g_gpio_cpuint = esp32_alloc_cpuint(1, ESP32_CPUINT_LEVEL);
DEBUGASSERT(g_gpio_cpuint >= 0);
/* Set up to receive peripheral interrupts on the current CPU */
/* Setup the GPIO interrupt. */
cpu = up_cpu_index();
/* Attach the GPIO peripheral to the allocated CPU interrupt */
esp32_attach_peripheral(cpu, ESP32_PERIPH_CPU_GPIO, g_gpio_cpuint);
g_gpio_cpuint = esp32_setup_irq(cpu, ESP32_PERIPH_CPU_GPIO,
1, ESP32_CPUINT_LEVEL);
DEBUGASSERT(g_gpio_cpuint >= 0);
/* Attach and enable the interrupt handler */

20
arch/xtensa/src/esp32/esp32_i2c.c
View File

@ -1554,7 +1554,12 @@ FAR struct i2c_master_s *esp32_i2cbus_initialize(int port)
#ifndef CONFIG_I2C_POLLED
config = priv->config;
priv->cpuint = esp32_alloc_cpuint(1, ESP32_CPUINT_LEVEL);
/* Set up to receive peripheral interrupts on the current CPU */
priv->cpu = up_cpu_index();
priv->cpuint = esp32_setup_irq(priv->cpu, config->periph,
1, ESP32_CPUINT_LEVEL);
if (priv->cpuint < 0)
{
/* Failed to allocate a CPU interrupt of this type */
@ -1564,16 +1569,10 @@ FAR struct i2c_master_s *esp32_i2cbus_initialize(int port)
return NULL;
}
/* Set up to receive peripheral interrupts on the current CPU */
priv->cpu = up_cpu_index();
esp32_attach_peripheral(priv->cpu, config->periph, priv->cpuint);
ret = irq_attach(config->irq, esp32_i2c_irq, priv);
if (ret != OK)
{
esp32_detach_peripheral(priv->cpu, config->periph, priv->cpuint);
esp32_free_cpuint(priv->cpuint);
esp32_teardown_irq(priv->cpu, config->periph, priv->cpuint);
leave_critical_section(flags);
@ -1624,10 +1623,7 @@ int esp32_i2cbus_uninitialize(FAR struct i2c_master_s *dev)
#ifndef CONFIG_I2C_POLLED
up_disable_irq(priv->config->irq);
esp32_detach_peripheral(priv->cpu,
priv->config->periph,
priv->cpuint);
esp32_free_cpuint(priv->cpuint);
esp32_teardown_irq(priv->cpu, priv->config->periph, priv->cpuint);
#endif
esp32_i2c_deinit(priv);

8
arch/xtensa/src/esp32/esp32_irq.c
View File

@ -132,14 +132,10 @@ static inline void xtensa_attach_fromcpu1_interrupt(void)
{
int cpuint;
/* Allocate a level-sensitive, priority 1 CPU interrupt for the UART */
cpuint = esp32_alloc_cpuint(1, ESP32_CPUINT_LEVEL);
DEBUGASSERT(cpuint >= 0);
/* Connect all CPU peripheral source to allocated CPU interrupt */
esp32_attach_peripheral(0, ESP32_PERIPH_CPU_CPU1, cpuint);
cpuint = esp32_setup_irq(0, ESP32_PERIPH_CPU_CPU1, 1, ESP32_CPUINT_LEVEL);
DEBUGASSERT(cpuint >= 0);
/* Attach the inter-CPU interrupt. */

50
arch/xtensa/src/esp32/esp32_serial.c
View File

@ -1013,9 +1013,11 @@ static int esp32_attach(struct uart_dev_s *dev)
struct esp32_dev_s *priv = (struct esp32_dev_s *)dev->priv;
int ret = OK;
/* Allocate a level-sensitive, priority 1 CPU interrupt for the UART */
/* Set up to receive peripheral interrupts on the current CPU */
priv->cpuint = esp32_alloc_cpuint(1, ESP32_CPUINT_LEVEL);
priv->cpu = up_cpu_index();
priv->cpuint = esp32_setup_irq(priv->cpu, priv->config->periph,
1, ESP32_CPUINT_LEVEL);
if (priv->cpuint < 0)
{
/* Failed to allocate a CPU interrupt of this type */
@ -1023,15 +1025,6 @@ static int esp32_attach(struct uart_dev_s *dev)
return priv->cpuint;
}
/* Set up to receive peripheral interrupts on the current CPU */
priv->cpu = up_cpu_index();
/* Attach the GPIO peripheral to the allocated CPU interrupt */
esp32_attach_peripheral(priv->cpu, priv->config->periph,
priv->cpuint);
/* Attach and enable the IRQ */
ret = irq_attach(priv->config->irq, esp32_interrupt, dev);
@ -1068,12 +1061,7 @@ static void esp32_detach(struct uart_dev_s *dev)
/* Disassociate the peripheral interrupt from the CPU interrupt */
esp32_detach_peripheral(priv->cpu, priv->config->periph,
priv->cpuint);
/* And release the CPU interrupt */
esp32_free_cpuint(priv->cpuint);
esp32_teardown_irq(priv->cpu, priv->config->periph, priv->cpuint);
priv->cpuint = -1;
}
@ -1140,21 +1128,6 @@ static void dma_attach(uint8_t dma_chan)
putreg32(UINT32_MAX, UHCI_INT_CLR_REG(dma_chan));
/* Allocate a level-sensitive, priority 1 CPU interrupt for the DMA */
dma_cpuint = esp32_alloc_levelint(1);
if (dma_cpuint < 0)
{
/* Failed to allocate a CPU interrupt of this type */
dmaerr("Failed to allocate a CPU interrupt.\n");
return;
}
/* Set up to receive peripheral interrupts on the current CPU */
cpu = up_cpu_index();
/* Attach the UHCI interrupt to the allocated CPU interrupt
* and attach and enable the IRQ.
*/
@ -1170,7 +1143,18 @@ static void dma_attach(uint8_t dma_chan)
irq = ESP32_IRQ_UHCI1;
}
esp32_attach_peripheral(cpu, periph, dma_cpuint);
/* Set up to receive peripheral interrupts on the current CPU */
cpu = up_cpu_index();
dma_cpuint = esp32_setup_irq(cpu, periph, 1, ESP32_CPUINT_LEVEL);
if (dma_cpuint < 0)
{
/* Failed to allocate a CPU interrupt of this type */
dmaerr("Failed to allocate a CPU interrupt.\n");
return;
}
ret = irq_attach(irq, esp32_interrupt_dma, NULL);
if (ret == OK)
{

27
arch/xtensa/src/esp32/esp32_spi.c
View File

@ -1464,27 +1464,23 @@ FAR struct spi_dev_s *esp32_spibus_initialize(int port)
if (priv->config->use_dma)
{
priv->cpuint = esp32_alloc_cpuint(1, ESP32_CPUINT_LEVEL);
/* Set up to receive peripheral interrupts on the current CPU */
priv->cpu = up_cpu_index();
priv->cpuint = esp32_setup_irq(priv->cpu, priv->config->periph,
1, ESP32_CPUINT_LEVEL);
if (priv->cpuint < 0)
{
leave_critical_section(flags);
return NULL;
}
/* Set up to receive peripheral interrupts on the current CPU */
priv->cpu = up_cpu_index();
esp32_attach_peripheral(priv->cpu,
priv->config->periph,
priv->cpuint);
ret = irq_attach(priv->config->irq, esp32_spi_interrupt, priv);
if (ret != OK)
{
esp32_detach_peripheral(priv->cpu,
priv->config->periph,
priv->cpuint);
esp32_free_cpuint(priv->cpuint);
esp32_teardown_irq(priv->cpu,
priv->config->periph,
priv->cpuint);
leave_critical_section(flags);
return NULL;
}
@ -1534,10 +1530,9 @@ int esp32_spibus_uninitialize(FAR struct spi_dev_s *dev)
if (priv->config->use_dma)
{
up_disable_irq(priv->config->irq);
esp32_detach_peripheral(priv->cpu,
priv->config->periph,
priv->cpuint);
esp32_free_cpuint(priv->cpuint);
esp32_teardown_irq(priv->cpu,
priv->config->periph,
priv->cpuint);
nxsem_destroy(&priv->sem_isr);
}

24
arch/xtensa/src/esp32/esp32_spi_slave.c
View File

@ -1296,28 +1296,16 @@ FAR struct spi_slave_ctrlr_s *esp32_spislv_ctrlr_initialize(int port)
esp32_io_interrupt,
priv));
priv->cpuint = esp32_alloc_cpuint(1, ESP32_CPUINT_LEVEL);
if (priv->cpuint < 0)
{
leave_critical_section(flags);
return NULL;
}
/* Set up to receive peripheral interrupts on the current CPU */
priv->cpu = up_cpu_index();
esp32_attach_peripheral(priv->cpu,
priv->config->periph,
priv->cpuint);
priv->cpuint = esp32_setup_irq(priv->cpu, priv->config->periph,
1, ESP32_CPUINT_LEVEL);
ret = irq_attach(priv->config->irq, esp32_spislv_interrupt, priv);
if (ret != OK)
{
esp32_detach_peripheral(priv->cpu,
priv->config->periph,
priv->cpuint);
esp32_free_cpuint(priv->cpuint);
esp32_teardown_irq(priv->cpu, priv->config->periph, priv->cpuint);
leave_critical_section(flags);
@ -1366,11 +1354,7 @@ int esp32_spislv_ctrlr_uninitialize(FAR struct spi_slave_ctrlr_s *ctrlr)
}
up_disable_irq(priv->config->irq);
esp32_detach_peripheral(priv->cpu,
priv->config->periph,
priv->cpuint);
esp32_free_cpuint(priv->cpuint);
esp32_teardown_irq(priv->cpu, priv->config->periph, priv->cpuint);
esp32_spislv_deinit(ctrlr);
leave_critical_section(flags);

28
arch/xtensa/src/esp32/esp32_tim.c
View File

@ -529,8 +529,7 @@ static int esp32_tim_setisr(FAR struct esp32_tim_dev_s *dev, xcpt_t handler,
*/
up_disable_irq(tim->irq);
esp32_detach_peripheral(tim->core, tim->periph, tim->cpuint);
esp32_free_cpuint(tim->cpuint);
esp32_teardown_irq(tim->core, tim->periph, tim->cpuint);
irq_detach(tim->irq);
tim->cpuint = -ENOMEM;
tim->core = -ENODEV;
@ -543,20 +542,16 @@ static int esp32_tim_setisr(FAR struct esp32_tim_dev_s *dev, xcpt_t handler,
{
if (tim->cpuint != -ENOMEM)
{
/* Disable the previous CPU Interrupt */
/* Disable the previous IRQ */
up_disable_irq(tim->irq);
/* Free cpu interrupt
* because we will get another from esp32_alloc_levelint
*/
esp32_free_cpuint(tim->cpuint);
}
/* Verify the available level CPU Interrupt */
/* Set up to receive peripheral interrupts on the current CPU */
tim->cpuint = esp32_alloc_cpuint(tim->priority, ESP32_CPUINT_LEVEL);
tim->core = up_cpu_index();
tim->cpuint = esp32_setup_irq(tim->core, tim->periph,
tim->priority, ESP32_CPUINT_LEVEL);
if (tim->cpuint < 0)
{
tmrerr("ERROR: No CPU Interrupt available");
@ -564,21 +559,12 @@ static int esp32_tim_setisr(FAR struct esp32_tim_dev_s *dev, xcpt_t handler,
goto errout;
}
/* Attach a peripheral interrupt to the available CPU interrupt in
* the current core
*/
tim->core = up_cpu_index();
esp32_attach_peripheral(tim->core, tim->periph, tim->cpuint);
/* Associate an IRQ Number (from the timer) to an ISR */
ret = irq_attach(tim->irq, handler, arg);
if (ret != OK)
{
esp32_detach_peripheral(tim->core, tim->periph, tim->cpuint);
esp32_free_cpuint(tim->cpuint);
esp32_teardown_irq(tim->core, tim->periph, tim->cpuint);
tmrerr("ERROR: Failed to associate an IRQ Number");
goto errout;
}

20
arch/xtensa/src/esp32/esp32_wdt.c
View File

@ -727,8 +727,7 @@ static int esp32_wdt_setisr(FAR struct esp32_wdt_dev_s *dev, xcpt_t handler,
*/
up_disable_irq(wdt->irq);
esp32_detach_peripheral(wdt->cpu, wdt->periph, wdt->cpuint);
esp32_free_cpuint(wdt->cpuint);
esp32_teardown_irq(wdt->cpu, wdt->periph, wdt->cpuint);
irq_detach(wdt->irq);
}
@ -740,9 +739,11 @@ static int esp32_wdt_setisr(FAR struct esp32_wdt_dev_s *dev, xcpt_t handler,
else
{
/* Verify the available CPU Interrupt */
/* Set up to receive peripheral interrupts on the current CPU */
wdt->cpuint = esp32_alloc_cpuint(1, ESP32_CPUINT_LEVEL);
wdt->cpu = up_cpu_index();
wdt->cpuint = esp32_setup_irq(wdt->cpu, wdt->periph,
1, ESP32_CPUINT_LEVEL);
if (wdt->cpuint < 0)
{
tmrerr("ERROR: No CPU Interrupt available");
@ -750,22 +751,13 @@ static int esp32_wdt_setisr(FAR struct esp32_wdt_dev_s *dev, xcpt_t handler,
goto errout;
}
wdt->cpu = up_cpu_index();
/* Attach a peripheral interrupt to the available CPU interrupt in
* the current core
*/
esp32_attach_peripheral(wdt->cpu, wdt->periph, wdt->cpuint);
/* Associate an IRQ Number (from the WDT) to an ISR */
ret = irq_attach(wdt->irq, handler, arg);
if (ret != OK)
{
esp32_detach_peripheral(wdt->cpu, wdt->periph, wdt->cpuint);
esp32_free_cpuint(wdt->cpuint);
esp32_teardown_irq(wdt->cpu, wdt->periph, wdt->cpuint);
tmrerr("ERROR: Failed to associate an IRQ Number");
goto errout;
}