sama5: add support for QSPI
This commit is contained in:
Janne Rosberg
Petro Karashchenko
parent
0f5cea7322
commit
03064b9701
@ -105,6 +105,7 @@
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#endif
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# define SAM_NDMAC 2 /* (2) XDMA controllers */
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# define SAM_NDMACHAN 16 /* (16) DMA channels per XDMA controller */
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# define SAM_NQSPI 2 /* (2) QuadSPI controllers */
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/* SAMA5D3 Family
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*
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@ -149,6 +149,14 @@ config SAMA5_HAVE_PIOE
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bool
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default n
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config SAMA5_HAVE_QSPI0
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bool
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default n
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config SAMA5_HAVE_QSPI1
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bool
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default n
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config SAMA5_HAVE_SAIC
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bool
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default n
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@ -250,7 +258,8 @@ config ARCH_CHIP_SAMA5D2
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select SAMA5_HAVE_FLEXCOM2
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select SAMA5_HAVE_FLEXCOM3
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select SAMA5_HAVE_FLEXCOM4
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select SAMA5_HAVE_QSPI
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select SAMA5_HAVE_QSPI0
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select SAMA5_HAVE_QSPI1
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select SAMA5_HAVE_XDMA
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select SAMA5_HAVE_SAIC
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select SAMA5_HAVE_SFC
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@ -651,6 +660,16 @@ config SAMA5_SPI2
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default n
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depends on SAMA5_HAVE_SPI2
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config SAMA5_QSPI0
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bool "Quad SPI interface 0 (QSPI0)"
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default n
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depends on SAMA5_HAVE_QSPI0
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config SAMA5_QSPI1
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bool "Quad SPI interface 1 (QSPI1)"
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default n
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depends on SAMA5_HAVE_QSPI1
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config SAMA5_TC0
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bool "Timer Counter 0 (ch. 0, 1, 2) (TC0)"
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default n
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@ -3459,6 +3478,53 @@ config SAMA5_FLEXCOM_SPI_DMADEBUG
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endmenu # Flexcom SPI device driver options
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endif # SAMA5_FLEXCOM0_SPI || SAMA5_FLEXCOM1_SPI || SAMA5_FLEXCOM2_SPI || SAMA5_FLEXCOM3_SPI || SAMA5_FLEXCOM4_SPI
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menu "QSPI Device Driver Configuration"
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depends on SAMA5_QSPI0 || SAMA5_QSPI1
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config SAMA5_QSPI_DLYBS
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int "Delay Before QSCK (nsec)"
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default 0
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config SAMA5_QSPI_DLYBCT
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int "Delay Between Consecutive Transfers (nsec)"
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default 0
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config SAMA5_QSPI_DMA
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bool "QSPI DMA"
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default n
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depends on SAMA5_XDMAC0 || SAMA5_XDMAC1
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---help---
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Use XDMA to improve SPI transfer performance.
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config SAMA5_QSPI_DMATHRESHOLD
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int "QSPI DMA threshold"
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default 4
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depends on SAMA5_QSPI_DMA
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---help---
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When QSPI (X)DMA is enabled, small DMA transfers will still be performed
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by polling logic. But we need a threshold value to determine what
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is small. That value is provided by SAMA5_QSPI_DMATHRESHOLD.
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config SAMA5_QSPI_DMADEBUG
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bool "QSPI DMA transfer debug"
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depends on SAMA5_QSPI_DMA && DEBUG_FEATURES && DEBUG_DMA
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default n
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---help---
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Enable special debug instrumentation analyze QSPI DMA data transfers.
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This logic is as non-invasive as possible: It samples DMA
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registers at key points in the data transfer and then dumps all of
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the registers at the end of the transfer.
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config SAMA5_QSPI_REGDEBUG
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bool "QSPI Register level debug"
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depends on DEBUG_SPI_INFO
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default n
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---help---
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Output detailed register-level QSPI device debug information.
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Requires also CONFIG_DEBUG_SPI_INFO.
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endmenu # QSPI Device Driver Configuration
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if SAMA5_TWI0 || SAMA5_TWI1 || SAMA5_TWI2 || SAMA5_TWI3 || SAMA5_FLEXCOM_TWI
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menu "TWI device driver options"
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@ -93,6 +93,14 @@ else
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endif
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endif
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ifeq ($(CONFIG_SAMA5_QSPI0),y)
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CHIP_CSRCS += sam_qspi.c
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else
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ifeq ($(CONFIG_SAMA5_QSPI1),y)
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CHIP_CSRCS += sam_qspi.c
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endif
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endif
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ifeq ($(CONFIG_SAMA5D2_CLASSD), y)
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CHIP_CSRCS += sam_classd.c
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endif
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266
arch/arm/src/sama5/hardware/sam_qspi.h
Normal file
266
arch/arm/src/sama5/hardware/sam_qspi.h
Normal file
@ -0,0 +1,266 @@
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/****************************************************************************
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* arch/arm/src/sama5/hardware/sam_qspi.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_QSPI_H
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#define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_QSPI_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <arch/sama5/chip.h>
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#include "hardware/sam_memorymap.h"
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#if SAM_NQSPI > 0 || SAM_NQSPI_SPI > 0
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* General Characteristics **************************************************/
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#define SAM_QSPI_MINBITS 8 /* Minimum word width */
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#define SAM_QSPI_MAXBITS 16 /* Maximum word width */
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/* QSPI register offsets ****************************************************/
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#define SAM_QSPI_CR_OFFSET 0x0000 /* Control Register */
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#define SAM_QSPI_MR_OFFSET 0x0004 /* Mode Register */
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#define SAM_QSPI_RDR_OFFSET 0x0008 /* Receive Data Register */
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#define SAM_QSPI_TDR_OFFSET 0x000c /* Transmit Data Register */
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#define SAM_QSPI_SR_OFFSET 0x0010 /* Status Register */
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#define SAM_QSPI_IER_OFFSET 0x0014 /* Interrupt Enable Register */
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#define SAM_QSPI_IDR_OFFSET 0x0018 /* Interrupt Disable Register */
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#define SAM_QSPI_IMR_OFFSET 0x001c /* Interrupt Mask Register */
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#define SAM_QSPI_SCR_OFFSET 0x0020 /* Serial Clock Register */
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#define SAM_QSPI_IAR_OFFSET 0x0030 /* Instruction Address Register */
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#define SAM_QSPI_ICR_OFFSET 0x0034 /* Instruction Code Register */
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#define SAM_QSPI_IFR_OFFSET 0x0038 /* Instruction Frame Register */
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/* 0x003c Reserved */
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#define SAM_QSPI_SMR_OFFSET 0x0040 /* Scrambling Mode Register */
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#define SAM_QSPI_SKR_OFFSET 0x0044 /* Scrambling Key Register */
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/* 0x0048–0x00e0 Reserved */
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#define SAM_QSPI_WPCR_OFFSET 0x00e4 /* Write Protection Control Register */
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#define SAM_QSPI_WPSR_OFFSET 0x00e8 /* Write Protection Status Register */
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/* 0xec-0xfc: Reserved */
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/* QSPI register addresses **************************************************/
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#define SAM_QSPI0_CR (SAM_QSPI0_BASE+SAM_QSPI_CR_OFFSET) /* Control Register */
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#define SAM_QSPI0_MR (SAM_QSPI0_BASE+SAM_QSPI_MR_OFFSET) /* Mode Register */
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#define SAM_QSPI0_RDR (SAM_QSPI0_BASE+SAM_QSPI_RDR_OFFSET) /* Receive Data Register */
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#define SAM_QSPI0_TDR (SAM_QSPI0_BASE+SAM_QSPI_TDR_OFFSET) /* Transmit Data Register */
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#define SAM_QSPI0_SR (SAM_QSPI0_BASE+SAM_QSPI_SR_OFFSET) /* Status Register */
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#define SAM_QSPI0_IER (SAM_QSPI0_BASE+SAM_QSPI_IER_OFFSET) /* Interrupt Enable Register */
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#define SAM_QSPI0_IDR (SAM_QSPI0_BASE+SAM_QSPI_IDR_OFFSET) /* Interrupt Disable Register */
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#define SAM_QSPI0_IMR (SAM_QSPI0_BASE+SAM_QSPI_IMR_OFFSET) /* Interrupt Mask Register */
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#define SAM_QSPI0_SCR (SAM_QSPI0_BASE+SAM_QSPI_SCR_OFFSET) /* Serial Clock Register */
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#define SAM_QSPI0_IAR (SAM_QSPI0_BASE+SAM_QSPI_IAR_OFFSET) /* Instruction Address Register */
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#define SAM_QSPI0_ICR (SAM_QSPI0_BASE+SAM_QSPI_ICR_OFFSET) /* Instruction Code Register */
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#define SAM_QSPI0_IFR (SAM_QSPI0_BASE+SAM_QSPI_IFR_OFFSET) /* Instruction Frame Register */
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#define SAM_QSPI0_SMR (SAM_QSPI0_BASE+SAM_QSPI_SMR_OFFSET) /* Scrambling Mode Register */
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#define SAM_QSPI0_SKR (SAM_QSPI0_BASE+SAM_QSPI_SKR_OFFSET) /* Scrambling Key Register */
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#define SAM_QSPI0_WPCR (SAM_QSPI0_BASE+SAM_QSPI_WPCR_OFFSET) /* Write Protection Control Register */
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#define SAM_QSPI0_WPSR (SAM_QSPI0_BASE+SAM_QSPI_WPSR_OFFSET) /* Write Protection Status Register */
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#if SAM_NQSPI > 1
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# define SAM_QSPI1_CR (SAM_QSPI1_BASE+SAM_QSPI_CR_OFFSET) /* Control Register */
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# define SAM_QSPI1_MR (SAM_QSPI1_BASE+SAM_QSPI_MR_OFFSET) /* Mode Register */
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# define SAM_QSPI1_RDR (SAM_QSPI1_BASE+SAM_QSPI_RDR_OFFSET) /* Receive Data Register */
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# define SAM_QSPI1_TDR (SAM_QSPI1_BASE+SAM_QSPI_TDR_OFFSET) /* Transmit Data Register */
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# define SAM_QSPI1_SR (SAM_QSPI1_BASE+SAM_QSPI_SR_OFFSET) /* Status Register */
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# define SAM_QSPI1_IER (SAM_QSPI1_BASE+SAM_QSPI_IER_OFFSET) /* Interrupt Enable Register */
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# define SAM_QSPI1_IDR (SAM_QSPI1_BASE+SAM_QSPI_IDR_OFFSET) /* Interrupt Disable Register */
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# define SAM_QSPI1_IMR (SAM_QSPI1_BASE+SAM_QSPI_IMR_OFFSET) /* Interrupt Mask Register */
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# define SAM_QSPI1_SCR (SAM_QSPI1_BASE+SAM_QSPI_SCR_OFFSET) /* Serial Clock Register */
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# define SAM_QSPI1_IAR (SAM_QSPI1_BASE+SAM_QSPI_IAR_OFFSET) /* Instruction Address Register */
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# define SAM_QSPI1_ICR (SAM_QSPI1_BASE+SAM_QSPI_ICR_OFFSET) /* Instruction Code Register */
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# define SAM_QSPI1_IFR (SAM_QSPI1_BASE+SAM_QSPI_IFR_OFFSET) /* Instruction Frame Register */
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# define SAM_QSPI1_SMR (SAM_QSPI1_BASE+SAM_QSPI_SMR_OFFSET) /* Scrambling Mode Register */
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# define SAM_QSPI1_SKR (SAM_QSPI1_BASE+SAM_QSPI_SKR_OFFSET) /* Scrambling Key Register */
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# define SAM_QSPI1_WPCR (SAM_QSPI1_BASE+SAM_QSPI_WPCR_OFFSET) /* Write Protection Control Register */
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# define SAM_QSPI1_WPSR (SAM_QSPI1_BASE+SAM_QSPI_WPSR_OFFSET) /* Write Protection Status Register */
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#endif
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/* QSPI register bit definitions ********************************************/
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/* QSPI Control Register */
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#define QSPI_CR_QSPIEN (1 << 0) /* Bit 0: QSPI Enable */
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#define QSPI_CR_QSPIDIS (1 << 1) /* Bit 1: QSPI Disable */
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#define QSPI_CR_SWRST (1 << 7) /* Bit 7: QSPI Software Reset */
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#define QSPI_CR_LASTXFER (1 << 24) /* Bit 24: Last Transfer */
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/* QSPI Mode Register */
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#define QSPI_MR_SPI (0 << 0) /* Bit 0: SPI Master Mode */
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#define QSPI_MR_SMM (1 << 0) /* Bit 0: Serial Memory Mode */
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#define QSPI_MR_LLB (1 << 1) /* Bit 1: Local Loopback Enable */
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#define QSPI_MR_WDRBT (1 << 2) /* Bit 2: Wait Data Read Before Transfer */
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#define QSPI_MR_CSMODE_SHIFT (4) /* Bits 4-5: Chip Select Mode */
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#define QSPI_MR_CSMODE_MASK (3 << QSPI_MR_CSMODE_SHIFT)
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# define QSPI_MR_CSMODE_NRELOAD (0 << QSPI_MR_CSMODE_SHIFT) /* CS deasserted if TD not reloaded */
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# define QSPI_MR_CSMODE_LASTXFER (1 << QSPI_MR_CSMODE_SHIFT) /* CS deasserted when LASTXFER transferred */
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# define QSPI_MR_CSMODE_SYSTEM (2 << QSPI_MR_CSMODE_SHIFT) /* CS deasserted after each transfer */
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#define QSPI_MR_NBBITS_SHIFT (8) /* Bits 8-11: Number Of Bits Per Transfer */
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#define QSPI_MR_NBBITS_MASK (15 << QSPI_MR_NBBITS_SHIFT)
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# define QSPI_MR_NBBITS(n) ((uint32_t)((n)-SAM_QSPI_MINBITS) << QSPI_MR_NBBITS_SHIFT)
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# define QSPI_MR_NBBITS_8BIT (0 << QSPI_MR_NBBITS_SHIFT) /* 8 bits for transfer */
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# define QSPI_MR_NBBITS_9BIT (1 << QSPI_MR_NBBITS_SHIFT) /* 9 bits for transfer */
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# define QSPI_MR_NBBITS_10BIT (2 << QSPI_MR_NBBITS_SHIFT) /* 10 bits for transfer */
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# define QSPI_MR_NBBITS_11BIT (3 << QSPI_MR_NBBITS_SHIFT) /* 11 bits for transfer */
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# define QSPI_MR_NBBITS_12BIT (4 << QSPI_MR_NBBITS_SHIFT) /* 12 bits for transfer */
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# define QSPI_MR_NBBITS_13BIT (5 << QSPI_MR_NBBITS_SHIFT) /* 13 bits for transfer */
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# define QSPI_MR_NBBITS_14BIT (6 << QSPI_MR_NBBITS_SHIFT) /* 14 bits for transfer */
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# define QSPI_MR_NBBITS_15BIT (7 << QSPI_MR_NBBITS_SHIFT) /* 15 bits for transfer */
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# define QSPI_MR_NBBITS_16BIT (8 << QSPI_MR_NBBITS_SHIFT) /* 16 bits for transfer */
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#define QSPI_MR_DLYBCT_SHIFT (16) /* Bits 16-23: Delay Between Consecutive Transfers */
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#define QSPI_MR_DLYBCT_MASK (0xff << QSPI_MR_DLYBCT_SHIFT)
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# define QSPI_MR_DLYBCT(n) ((uint32_t)(n) << QSPI_MR_DLYBCT_SHIFT)
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#define QSPI_MR_DLYCS_SHIFT (24) /* Bits 24-31: Minimum Inactive QCS Delay */
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#define QSPI_MR_DLYCS_MASK (0xff << QSPI_MR_DLYCS_SHIFT)
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# define QSPI_MR_DLYCS(n) ((uint32_t)(n) << QSPI_MR_DLYCS_SHIFT)
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/* QSPI Receive Data Register */
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#define QSPI_RDR_RD_SHIFT (0) /* Bits 0-15: Receive Data */
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#define QSPI_RDR_RD_MASK (0xffff << QSPI_RDR_RD_SHIFT)
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/* QSPI Transmit Data Register */
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#define QSPI_TDR_TD_SHIFT (0) /* Bits 0-15: Transmit Data */
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#define QSPI_TDR_TD_MASK (0xffff << QSPI_TDR_TD_SHIFT)
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/* QSPI Status Register, QSPI Interrupt Enable Register,
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* QSPI Interrupt Disable Register,
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* and QSPI Interrupt Mask Register (common bit fields)
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*/
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#define QSPI_INT_RDRF (1 << 0) /* Bit 0: Receive Data Register Full Interrupt */
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#define QSPI_INT_TDRE (1 << 1) /* Bit 1: Transmit Data Register Empty Interrupt */
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#define QSPI_INT_TXEMPTY (1 << 2) /* Bit 2: Transmission Registers Empty Interrupt */
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#define QSPI_INT_OVRES (1 << 3) /* Bit 3: Overrun Error Interrupt */
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#define QSPI_INT_CSR (1 << 8) /* Bit 8: Chip Select Rise Interrupt */
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#define QSPI_SR_CSS (1 << 9) /* Bit 9: Chip Select Status Interrupt */
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#define QSPI_SR_INSTRE (1 << 10) /* Bit 10: Instruction End Status Interrupt */
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#define QSPI_SR_QSPIENS (1 << 24) /* Bit 24: QSPI Enable Status (SR only) */
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#define QSPI_INT_ALL (0x0000070f)
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/* Serial Clock Register */
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#define QSPI_SCR_CPOL (1 << 0) /* Bit 0: Clock Polarity */
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#define QSPI_SCR_CPHA (1 << 1) /* Bit 1: Clock Phase */
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#define QSPI_SCR_SCBR_SHIFT (8) /* Bits 8-15: Serial Clock Baud Rate */
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#define QSPI_SCR_SCBR_MASK (0xff << QSPI_SCR_SCBR_SHIFT)
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# define QSPI_SCR_SCBR(n) ((uint32_t)(n) << QSPI_SCR_SCBR_SHIFT)
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#define QSPI_SCR_DLYBS_SHIFT (16) /* Bits 16-23: Delay Before QSCK */
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#define QSPI_SCR_DLYBS_MASK (0xff << QSPI_SCR_DLYBS_SHIFT)
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# define QSPI_SCR_DLYBS(n) ((uint32_t)(n) << QSPI_SCR_DLYBS_SHIFT)
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/* Instruction Address Register (32-bit value) */
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/* Instruction Code Register */
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#define QSPI_ICR_INST_SHIFT (0) /* Bits 0-7: Instruction Code */
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#define QSPI_ICR_INST_MASK (0xff << QSPI_ICR_INST_SHIFT)
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# define QSPI_ICR_INST(n) ((uint32_t)(n) << QSPI_ICR_INST_SHIFT)
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#define QSPI_ICR_OPT_SHIFT (16) /* Bits 16-23: Option Code */
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#define QSPI_ICR_OPT_MASK (0xff << QSPI_ICR_OPT_SHIFT)
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# define QSPI_ICR_OPT(n) ((uint32_t)(n) << QSPI_ICR_OPT_SHIFT)
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/* Instruction Frame Register */
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#define QSPI_IFR_WIDTH_SHIFT (0) /* Bits 0-2: Width of Instruction Code,
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* Address, Option Code and Data */
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#define QSPI_IFR_WIDTH_MASK (7 << QSPI_IFR_WIDTH_SHIFT)
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/* Instruction Address-Option Data */
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# define QSPI_IFR_WIDTH_SINGLE (0 << QSPI_IFR_WIDTH_SHIFT) /* Single-bit Single-bit Single-bit */
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# define QSPI_IFR_WIDTH_DUALOUT (1 << QSPI_IFR_WIDTH_SHIFT) /* Single-bit Single-bit Dual */
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# define QSPI_IFR_WIDTH_QUADOUT (2 << QSPI_IFR_WIDTH_SHIFT) /* Single-bit Single-bit Quad */
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# define QSPI_IFR_WIDTH_DUALIO (3 << QSPI_IFR_WIDTH_SHIFT) /* Single-bit Dual Dual */
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# define QSPI_IFR_WIDTH_QUADIO (4 << QSPI_IFR_WIDTH_SHIFT) /* Single-bit Quad Quad */
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# define QSPI_IFR_WIDTH_DUALCMD (5 << QSPI_IFR_WIDTH_SHIFT) /* Dual Dual Dual */
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# define QSPI_IFR_WIDTH_QUADCMD (6 << QSPI_IFR_WIDTH_SHIFT) /* Quad Quad Quad */
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#define QSPI_IFR_INSTEN (1 << 4) /* Bit 4: Instruction Enable */
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#define QSPI_IFR_ADDREN (1 << 5) /* Bit 5: Address Enable */
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#define QSPI_IFR_OPTEN (1 << 6) /* Bit 6: Option Enable */
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#define QSPI_IFR_DATAEN (1 << 7) /* Bit 7: Data Enable */
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#define QSPI_IFR_OPTL_SHIFT (8) /* Bits 8-9: Option Code Length */
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#define QSPI_IFR_OPTL_MASK (3 << QSPI_IFR_OPTL_SHIFT)
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# define QSPI_IFR_OPTL_1BIT (0 << QSPI_IFR_OPTL_SHIFT) /* Option is 1 bit */
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# define QSPI_IFR_OPTL_2BIT (1 << QSPI_IFR_OPTL_SHIFT) /* Option is 2 bits */
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# define QSPI_IFR_OPTL_4BIT (2 << QSPI_IFR_OPTL_SHIFT) /* Option is 4 bits */
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# define QSPI_IFR_OPTL_8BIT (3 << QSPI_IFR_OPTL_SHIFT) /* Option is 8 bits */
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#define QSPI_IFR_ADDRL (1 << 10) /* Bit 10: Address Length */
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# define QSPI_IFR_ADDRL_24BIT (0 << 10) /* 0=24-bit */
|
||||
# define QSPI_IFR_ADDRL_32BIT (1 << 10) /* 1=32-bit */
|
||||
#define QSPI_IFR_TFRTYP_SHIFT (12) /* Bits 12-13: Data Transfer Type */
|
||||
#define QSPI_IFR_TFRTYP_MASK (3 << QSPI_IFR_TFRTYP_SHIFT)
|
||||
# define QSPI_IFR_TFRTYP_READ (0 << QSPI_IFR_TFRTYP_SHIFT) /* Read transfer from serial memory */
|
||||
# define QSPI_IFR_TFRTYP_RDMEM (1 << QSPI_IFR_TFRTYP_SHIFT) /* Read data transfer from serial memory */
|
||||
# define QSPI_IFR_TFRTYP_WRITE (2 << QSPI_IFR_TFRTYP_SHIFT) /* Write transfer into serial memory */
|
||||
# define QSPI_IFR_TFRTYP_WRMEM (3 << QSPI_IFR_TFRTYP_SHIFT) /* Write data transfer the serial memory */
|
||||
|
||||
#define QSPI_IFR_CRM (1 << 14) /* Bit 14: Continuous Read Mode */
|
||||
#define QSPI_IFR_NBDUM_SHIFT (16) /* Bits 16-20: Number Of Dummy Cycles */
|
||||
#define QSPI_IFR_NBDUM_MASK (31 << QSPI_IFR_NBDUM_SHIFT)
|
||||
# define QSPI_IFR_NBDUM(n) ((uint32_t)(n) << QSPI_IFR_NBDUM_SHIFT)
|
||||
|
||||
/* Scrambling Mode Register */
|
||||
|
||||
#define QSPI_SMR_SCREN (1 << 0) /* Bit 0: Scrambling/Unscrambling Enable */
|
||||
#define QSPI_SMR_RVDIS (1 << 1) /* Bit 1: Scrambling/Unscrambling Random Value Disable */
|
||||
|
||||
/* Scrambling Key Register (32-bit value) */
|
||||
|
||||
/* QSPI Write Protection Control Register */
|
||||
|
||||
#define QSPI_WPCR_WPEN (1 << 0) /* Bit 0: QSPI Write Protection Enable */
|
||||
#define QSPI_WPCR_WPKEY_SHIFT (8) /* Bits 8-31: QSPI Write Protection Key Password */
|
||||
#define QSPI_WPCR_WPKEY_MASK (0x00ffffff << QSPI_WPCR_WPKEY_SHIFT)
|
||||
# define QSPI_WPCR_WPKEY (0x00515350 << QSPI_WPCR_WPKEY_SHIFT)
|
||||
|
||||
/* QSPI Write Protection Status Register */
|
||||
|
||||
#define QSPI_WPSR_WPVS (1 << 0) /* Bit 0: QSPI Write Protection Violation Status */
|
||||
#define QSPI_WPSR_WPVSRC_SHIFT (8) /* Bits 8-15: QSPI Write Protection Violation Source */
|
||||
#define QSPI_WPSR_WPVSRC_MASK (0xff << QSPI_WPSR_WPVSRC_SHIFT)
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
#endif /* SAM_NQSPI > 0 */
|
||||
#endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_QSPI_H */
|
||||
1907
arch/arm/src/sama5/sam_qspi.c
Normal file
1907
arch/arm/src/sama5/sam_qspi.c
Normal file
File diff suppressed because it is too large
Load Diff
90
arch/arm/src/sama5/sam_qspi.h
Normal file
90
arch/arm/src/sama5/sam_qspi.h
Normal file
@ -0,0 +1,90 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/sama5/sam_qspi.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_SAMA5_SAM_QSPI_H
|
||||
#define __ARCH_ARM_SRC_SAMA5_SAM_QSPI_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "sam_config.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Inline Functions
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_qspi_initialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize the selected QSPI port in master mode
|
||||
*
|
||||
* Input Parameters:
|
||||
* intf - Interface number(must be zero)
|
||||
*
|
||||
* Returned Value:
|
||||
* Valid SPI device structure reference on success; a NULL on failure
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
struct qspi_dev_s;
|
||||
struct qspi_dev_s *sam_qspi_initialize(int intf);
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_SAMA5_SAM_QSPI_H */
|
||||
Loading…
Reference in New Issue
Block a user