arch/risc-v: Don't clear reserved bits in fcsr in riscv_fpuconfig

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-04-21 12:23:18 +08:00 · 2022-04-21 12:23:18 +08:00 · 0332b78f99
commit 0332b78f99
parent 875c5dac75
1 changed files with 5 additions and 1 deletions
--- a/arch/risc-v/src/common/riscv_fpu.S
+++ b/arch/risc-v/src/common/riscv_fpu.S
@ -64,7 +64,11 @@
 riscv_fpuconfig:
    li           a0, MSTATUS_FS_INIT
    csrs         CSR_STATUS, a0
-    csrwi        fcsr, 0
+
+    fsflags      zero
+    fsrm         zero
+
+    fence.i
    ret

 #endif /* CONFIG_ARCH_FPU */