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Run indent.sh agains lpc2378 code

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2588 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2010-04-11 19:17:03 +00:00
parent ea7865a89e
commit 03a78173be
8 changed files with 575 additions and 542 deletions
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1
arch/arm/include/lpc2378/irq.h
View File

@ -48,6 +48,7 @@
/****************************************************************************
* Included Files
****************************************************************************/
#ifndef __ASSEMBLY__
# include <stdint.h>
#endif

37
arch/arm/src/lpc2378/lpc23xx_decodeirq.c
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@ -107,7 +107,7 @@
#ifndef CONFIG_VECTORED_INTERRUPTS
void up_decodeirq(uint32_t *regs)
#else
static void lpc23xx_decodeirq( uint32_t *regs)
static void lpc23xx_decodeirq(uint32_t *regs)
#endif
{
#ifdef CONFIG_SUPPRESS_INTERRUPTS
@ -118,28 +118,30 @@ static void lpc23xx_decodeirq( uint32_t *regs)
/* Check which IRQ fires */
uint32_t irqbits = vic_getreg(VIC_IRQSTATUS_OFFSET) & 0xFFFFFFFF;
unsigned int irq;
for (irq = 0; irq < NR_IRQS; irq++)
{
if( irqbits & (uint32_t)(1<<irq) ) break;
}
uint32_t irqbits = vic_getreg(VIC_IRQSTATUS_OFFSET) & 0xFFFFFFFF;
unsigned int irq;
for (irq = 0; irq < NR_IRQS; irq++)
{
if (irqbits & (uint32_t) (1 << irq))
break;
}
/* Verify that the resulting IRQ number is valid */
if (irq < NR_IRQS) /* redundant check ?? */
if (irq < NR_IRQS) /* redundant check ?? */
{
/* Current regs non-zero indicates that we are processing an interrupt;
* current_regs is also used to manage interrupt level context switches.
*/
DEBUGASSERT(current_regs == NULL);
current_regs = regs;
/* Mask and acknowledge the interrupt */
up_maskack_irq(irq);
/* Deliver the IRQ */
irq_dispatch(irq, regs);
@ -155,14 +157,15 @@ static void lpc23xx_decodeirq( uint32_t *regs)
#ifdef CONFIG_VECTORED_INTERRUPTS
void up_decodeirq(uint32_t *regs)
{
vic_vector_t vector = (vic_vector_t)vic_getreg(VIC_ADDRESS_OFFSET);
vic_vector_t vector = (vic_vector_t) vic_getreg(VIC_ADDRESS_OFFSET);
/* Mask and acknowledge the interrupt */
up_maskack_irq(irq);
up_maskack_irq(irq);
/* Valid Interrupt */
if(vector != NULL)
(vector)(regs);
if (vector != NULL)
(vector) (regs);
}
#endif

1
arch/arm/src/lpc2378/lpc23xx_head.S
View File

@ -122,7 +122,6 @@ _vector_table:
.long up_vectorfiq
.size _vector_table, . - _vector_table
/****************************************************************************
* OS Entry Point
****************************************************************************/

76
arch/arm/src/lpc2378/lpc23xx_io.c
View File

@ -52,42 +52,50 @@
* Definitions
***********************************************************************/
/******************************************************************************
* Name: IO_Init()
/***********************************************************************
* Name: IO_Init()
*
* Descriptions: Initialize the target board before running the main()
* Descriptions: Initialize the target board before running the main()
*
******************************************************************************/
************************************************************************/
void IO_Init( void )
{
uint32_t regval;
/* Reset all GPIO pins to default */
pinsel_putreg(0, PINSEL0_OFFSET);
pinsel_putreg(0, PINSEL1_OFFSET);
pinsel_putreg(0, PINSEL2_OFFSET);
pinsel_putreg(0, PINSEL3_OFFSET);
pinsel_putreg(0, PINSEL4_OFFSET);
pinsel_putreg(0, PINSEL5_OFFSET);
pinsel_putreg(0, PINSEL6_OFFSET);
pinsel_putreg(0, PINSEL7_OFFSET);
pinsel_putreg(0, PINSEL8_OFFSET);
pinsel_putreg(0, PINSEL9_OFFSET);
pinsel_putreg(0, PINSEL10_OFFSET);
/*
regval = scb_getreg(SCB_PCONP_OFFSET) & \
~(PCSDC | PCUART1 | PCI2C0 | PCSSP1 | PCEMC | );
scb_getreg( regval, SCB_PCONP_OFFSET );
*/
/* Turn off all peripheral power */
scb_putreg( 0, SCB_PCONP_OFFSET );
/* Turn on UART0/2 / Timer0 */
//~ regval = PCUART0 | PCUART2 | PCTIM0 | PCRTC ;
regval = PCUART0 | PCUART2 | PCTIM0 ;
scb_putreg( regval , SCB_PCONP_OFFSET );
/* Status LED P1.19 */
dir_putreg8((1 << 3), FIO1DIR2_OFFSET);
/* other io setup here */
return;
uint32_t regval;
/* Reset all GPIO pins to default */
pinsel_putreg(0, PINSEL0_OFFSET);
pinsel_putreg(0, PINSEL1_OFFSET);
pinsel_putreg(0, PINSEL2_OFFSET);
pinsel_putreg(0, PINSEL3_OFFSET);
pinsel_putreg(0, PINSEL4_OFFSET);
pinsel_putreg(0, PINSEL5_OFFSET);
pinsel_putreg(0, PINSEL6_OFFSET);
pinsel_putreg(0, PINSEL7_OFFSET);
pinsel_putreg(0, PINSEL8_OFFSET);
pinsel_putreg(0, PINSEL9_OFFSET);
pinsel_putreg(0, PINSEL10_OFFSET);
/*
regval = scb_getreg(SCB_PCONP_OFFSET) & ~(PCSDC | PCUART1 | PCI2C0 | PCSSP1 | PCEMC | );
scb_getreg(regval, SCB_PCONP_OFFSET );
*/
/* Turn off all peripheral power */
scb_putreg(0, SCB_PCONP_OFFSET );
/* Turn on UART0/2 / Timer0 */
/* regval = PCUART0 | PCUART2 | PCTIM0 | PCRTC ; */
regval = PCUART0 | PCUART2 | PCTIM0 ;
scb_putreg(regval , SCB_PCONP_OFFSET );
/* Status LED P1.19 */
dir_putreg8((1 << 3), FIO1DIR2_OFFSET);
/* other io setup here */
return;
}

79
arch/arm/src/lpc2378/lpc23xx_irq.c
View File

@ -85,23 +85,25 @@ uint32_t *current_regs;
void up_irqinitialize(void)
{
int reg;
int reg;
/* Disable all interrupts. We do this by writing ones to the IntClearEnable
* register.
*/
vic_putreg(0xffffffff, VIC_INTENCLEAR_OFFSET);
/* Select all IRQs, FIQs are not used */
vic_putreg(0, VIC_INTSELECT_OFFSET);
/* Clear priority interrupts */
for (reg = 0; reg < NR_IRQS; reg++)
{
vic_putreg(0, VIC_VECTADDR0_OFFSET + (reg << 2));
vic_putreg(0x0F, VIC_VECTPRIORITY0_OFFSET + (reg << 2));
}
{
vic_putreg(0, VIC_VECTADDR0_OFFSET + (reg << 2));
vic_putreg(0x0F, VIC_VECTPRIORITY0_OFFSET + (reg << 2));
}
/* currents_regs is non-NULL only while processing an interrupt */
@ -113,25 +115,29 @@ void up_irqinitialize(void)
irqrestore(SVC_MODE | PSR_F_BIT);
#endif
}
/***********************************************************************
* Name: up_enable_irq_protect
* VIC registers can be accessed in User or privileged mode
***********************************************************************/
static void up_enable_irq_protect(void)
{
//~ uint32_t reg32 = vic_getreg(VIC_PROTECTION_OFFSET);
//~ reg32 &= ~(0xFFFFFFFF);
vic_putreg(0x01, VIC_PROTECTION_OFFSET);
// ~ uint32_t reg32 = vic_getreg(VIC_PROTECTION_OFFSET);
// ~ reg32 &= ~(0xFFFFFFFF);
vic_putreg(0x01, VIC_PROTECTION_OFFSET);
}
/***********************************************************************
* Name: up_disable_irq_protect
* VIC registers can only be accessed in privileged mode
***********************************************************************/
static void up_disable_irq_protect(void)
{
vic_putreg(0, VIC_PROTECTION_OFFSET);
vic_putreg(0, VIC_PROTECTION_OFFSET);
}
/***********************************************************************
* Name: up_disable_irq
*
@ -146,8 +152,8 @@ void up_disable_irq(int irq)
if (irq < NR_IRQS)
{
/* Disable the irq by setting the corresponding bit in the VIC
* Interrupt Enable Clear register.
/* Disable the irq by setting the corresponding bit in the VIC Interrupt
* Enable Clear register.
*/
vic_putreg((1 << irq), VIC_INTENCLEAR_OFFSET);
@ -172,8 +178,8 @@ void up_enable_irq(int irq)
irqstate_t flags = irqsave();
/* Enable the irq by setting the corresponding bit in the VIC
* Interrupt Enable register.
/* Enable the irq by setting the corresponding bit in the VIC Interrupt
* Enable register.
*/
uint32_t val = vic_getreg(VIC_INTENABLE_OFFSET);
@ -196,16 +202,21 @@ void up_maskack_irq(int irq)
if ((unsigned)irq < NR_IRQS)
{
/* Mask the IRQ by clearing the associated bit in Software Priority Mask register */
reg32 = vic_getreg(VIC_PRIORITY_MASK_OFFSET);
reg32 &= ~(1 << irq);
vic_putreg(reg32, VIC_PRIORITY_MASK_OFFSET);
/* Mask the IRQ by clearing the associated bit in Software Priority Mask
* register
*/
reg32 = vic_getreg(VIC_PRIORITY_MASK_OFFSET);
reg32 &= ~(1 << irq);
vic_putreg(reg32, VIC_PRIORITY_MASK_OFFSET);
}
/* Clear interrupt */
vic_putreg((1<<irq), VIC_SOFTINTCLEAR_OFFSET);
/* Clear interrupt */
vic_putreg((1 << irq), VIC_SOFTINTCLEAR_OFFSET);
#ifdef CONFIG_VECTORED_INTERRUPTS
vic_putreg(0, VIC_ADDRESS_OFFSET); /* dummy write to clear VICADDRESS */
#endif
vic_putreg(0, VIC_ADDRESS_OFFSET); /* dummy write to clear VICADDRESS */
#endif
}
/****************************************************************************
@ -218,13 +229,13 @@ void up_maskack_irq(int irq)
int up_prioritize_irq(int irq, int priority)
{
/* The default priority on reset is 16 */
if (irq < NR_IRQS && priority > 0 && priority < 16)
{
int offset = irq << 2;
vic_putreg( priority, VIC_VECTPRIORITY0_OFFSET + offset );
return OK;
}
/* The default priority on reset is 16 */
if (irq < NR_IRQS && priority > 0 && priority < 16)
{
int offset = irq << 2;
vic_putreg(priority, VIC_VECTPRIORITY0_OFFSET + offset);
return OK;
}
return -EINVAL;
}
@ -251,17 +262,17 @@ void up_attach_vector(int irq, int vector, vic_vector_t handler)
/* Save the vector address */
vic_putreg((uint32_t)handler, VIC_VECTADDR0_OFFSET + offset);
/* Set the interrupt priority */
vic_putreg((uint32_t) handler, VIC_VECTADDR0_OFFSET + offset);
/* Set the interrupt priority */
up_prioritize_irq(irq, vector);
/* Enable the vectored interrupt */
uint32_t val = vic_getreg(VIC_INTENABLE_OFFSET);
vic_putreg(val | (1 << irq), VIC_INTENABLE_OFFSET);
irqrestore(flags);
}
}

172
arch/arm/src/lpc2378/lpc23xx_pllsetup.c
View File

@ -71,22 +71,24 @@
#include "lpc23xx_scb.h"
extern void IO_Init(void);
/***********************************************************************
* Definitions
**********************************************************************/
#if ((FOSC < 32000) || (FOSC > 50000000))
# error Fosc out of range (32KHz-50MHz)
# error correct and recompile
# error Fosc out of range (32KHz-50MHz)
# error correct and recompile
#endif
#if ((CCLK < 10000000) || (CCLK > 72000000))
# error cclk out of range (10MHz-72MHz)
# error correct PLL MULTIPLIER and recompile
# error cclk out of range (10MHz-72MHz)
# error correct PLL MULTIPLIER and recompile
#endif
#if ((FCCO < 275000000) || (FCCO > 550000000))
# error Fcco out of range (275MHz-550MHz)
# error internal algorithm error
# error Fcco out of range (275MHz-550MHz)
# error internal algorithm error
#endif
/* Phase Locked Loop (PLL) initialization values
@ -95,23 +97,25 @@ extern void IO_Init(void);
* CCLK = 57 600 000 Hz
* Bit 16:23 NSEL: PLL Divider "N" Value
* Fcco = (2 * M * F_in) / N
* 275MHz <= Fcco <= 550MHz
* 275MHz <= Fcco <= 550MHz
*
* PLL clock sources:
* Internal RC 0 default on reset
* Main Oscillator 1
* RTC 2
* Internal RC 0 default on reset
* Main Oscillator 1
* RTC 2
*/
#ifdef CONFIG_PLL_CLKSRC
# if ( (CONFIG_PLL_CLKSRC < 0) || (CONFIG_PLL_CLKSRC > 2) )
# error "PLL clock source not valid, check configuration "
# endif
# if ( (CONFIG_PLL_CLKSRC < 0) || (CONFIG_PLL_CLKSRC > 2) )
# error "PLL clock source not valid, check configuration "
# endif
#else
# error "PLL clock source not defined, check configuration file"
# error "PLL clock source not defined, check configuration file"
#endif
/* PLL provides CCLK and must always be configured */
#define PLL ( PLL_M | (PLL_N << 16) )
#define PLL ( PLL_M | (PLL_N << 16) )
/* Memory Accelerator Module (MAM) initialization values
*
@ -131,108 +135,108 @@ extern void IO_Init(void);
* 6 = 6 CCLK
* 7 = 7 CCLK
*/
/* LPC2378 Rev. '-' errata MAM may not work if fully enabled */
#ifdef CONFIG_MAM_SETUP
# ifndef CONFIG_MAMCR_VALUE /* Can be selected from config file */
# define CONFIG_MAMCR_VALUE (MAMCR_PART)
# endif
# ifndef CONFIG_MAMTIM_VALUE /* Can be selected from config file */
# define CONFIG_MAMTIM_VALUE (0x00000003)
# endif
/* LPC2378 Rev. '-' errata MAM may not work if fully enabled */
#ifdef CONFIG_MAM_SETUP
# ifndef CONFIG_MAMCR_VALUE /* Can be selected from config file */
# define CONFIG_MAMCR_VALUE (MAMCR_PART)
# endif
# ifndef CONFIG_MAMTIM_VALUE /* Can be selected from config file */
# define CONFIG_MAMTIM_VALUE (0x00000003)
# endif
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: up_scbpllfeed
****************************************************************************/
static inline void up_scbpllfeed(void)
{
SCB_PLLFEED = 0xAA;
SCB_PLLFEED = 0x55;
SCB_PLLFEED = 0xAA;
SCB_PLLFEED = 0x55;
}
/****************************************************************************
* Name: ConfigurePLL
****************************************************************************/
void ConfigurePLL ( void )
void ConfigurePLL(void)
{
uint32_t MSel, NSel;
/* LPC2378 Rev.'-' errata Enable the Ethernet block to enable 16k EnetRAM */
SCB_PCONP |= PCENET;
/* Vectors are remapped to Flash */
SCB_MEMMAP = MEMMAP2FLASH;
/* Enable PLL, disconnected */
if(SCB_PLLSTAT & (1 << 25))
{
SCB_PLLCON = 0x01;
up_scbpllfeed();
}
uint32_t MSel, NSel;
/* Disable PLL, disconnected */
SCB_PLLCON = 0;
up_scbpllfeed();
/* LPC2378 Rev.'-' errata Enable the Ethernet block to enable 16k EnetRAM */
SCB_PCONP |= PCENET;
/* Enable main OSC */
SCB_SCS |= 0x20;
/* Vectors are remapped to Flash */
SCB_MEMMAP = MEMMAP2FLASH;
/* Wait until main OSC is usable */
while( !(SCB_SCS & 0x40) );
/* Enable PLL, disconnected */
if (SCB_PLLSTAT & (1 << 25))
{
SCB_PLLCON = 0x01;
up_scbpllfeed();
}
/* Disable PLL, disconnected */
SCB_PLLCON = 0;
up_scbpllfeed();
/* select main OSC, 12MHz, as the PLL clock source */
SCB_CLKSRCSEL = CONFIG_PLL_CLKSRC;
/* Enable main OSC */
SCB_SCS |= 0x20;
/* Reconfigure PLL */
SCB_PLLCFG = PLL;
up_scbpllfeed();
/* Wait until main OSC is usable */
while (!(SCB_SCS & 0x40));
/* select main OSC, 12MHz, as the PLL clock source */
SCB_CLKSRCSEL = CONFIG_PLL_CLKSRC;
/* Enable PLL */
SCB_PLLCON = 0x01;
up_scbpllfeed();
/* Reconfigure PLL */
SCB_PLLCFG = PLL;
up_scbpllfeed();
/* Set clock divider */
SCB_CCLKCFG = CCLK_DIV;
/* Enable PLL */
SCB_PLLCON = 0x01;
up_scbpllfeed();
/* Set clock divider */
SCB_CCLKCFG = CCLK_DIV;
#ifdef CONFIG_USBDEV
/* usbclk = 288 MHz/6 = 48 MHz */
SCB_USBCLKCFG = USBCLK_DIV;
/* Turn On USB PCLK */
SCB_PCONP |= PCUSB;
/* usbclk = 288 MHz/6 = 48 MHz */
SCB_USBCLKCFG = USBCLK_DIV;
/* Turn On USB PCLK */
SCB_PCONP |= PCUSB;
#endif
/* Wait for PLL to lock */
while( ( SCB_PLLSTAT & (1 << 26) ) == 0);
/* Wait for PLL to lock */
while ((SCB_PLLSTAT & (1 << 26)) == 0);
MSel = SCB_PLLSTAT & 0x00007FFF;
NSel = ( SCB_PLLSTAT & 0x00FF0000 ) >> 16;
while( (MSel != PLL_M) && (NSel != PLL_N) );
/* Enable and connect */
SCB_PLLCON = 0x03;
up_scbpllfeed();
/* Check connect bit status */
while( ( SCB_PLLSTAT & ( 1 << 25 ) ) == 0 );
MSel = SCB_PLLSTAT & 0x00007FFF;
NSel = (SCB_PLLSTAT & 0x00FF0000) >> 16;
while ((MSel != PLL_M) && (NSel != PLL_N));
/* Set memory accelerater module*/
SCB_MAMCR = 0;
SCB_MAMTIM = CONFIG_MAMTIM_VALUE;
SCB_MAMCR = CONFIG_MAMCR_VALUE;
/* Enable and connect */
SCB_PLLCON = 0x03;
up_scbpllfeed();
/* Enable FastIO on P0:P1 */
SCB_SCS |= 0x01;
IO_Init();
return;
/* Check connect bit status */
while ((SCB_PLLSTAT & (1 << 25)) == 0);
/* Set memory accelerater module */
SCB_MAMCR = 0;
SCB_MAMTIM = CONFIG_MAMTIM_VALUE;
SCB_MAMCR = CONFIG_MAMCR_VALUE;
/* Enable FastIO on P0:P1 */
SCB_SCS |= 0x01;
IO_Init();
return;
}

666
arch/arm/src/lpc2378/lpc23xx_serial.c
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File diff suppressed because it is too large Load Diff

85
arch/arm/src/lpc2378/lpc23xx_timerisr.c
View File

@ -56,33 +56,30 @@
#include "lpc23xx_vic.h"
#include "lpc23xx_timer.h"
/****************************************************************************
* Definitions
****************************************************************************/
/* T0_PCLKDIV valid values are 1,2,4 */
#define T0_PCLK_DIV 1
/* PCKLSEL0 bits 3:2, 00=CCLK/4, 01=CCLK/1 , 10=CCLK/2 */
#ifdef T0_PCLK_DIV
# if T0_PCLK_DIV == 1
# define TIMER0_PCLKSEL (0x00000004)
# elif T0_PCLK_DIV == 2
# define TIMER0_PCLKSEL (0x00000008)
# elif T0_PCLK_DIV == 4
# define TIMER0_PCLKSEL (0x00000000)
# endif
# if T0_PCLK_DIV == 1
# define TIMER0_PCLKSEL (0x00000004)
# elif T0_PCLK_DIV == 2
# define TIMER0_PCLKSEL (0x00000008)
# elif T0_PCLK_DIV == 4
# define TIMER0_PCLKSEL (0x00000000)
# endif
#endif
#define T0_PCLKSEL_MASK (0x0000000C)
#define T0_TICKS_COUNT ( (CCLK / T0_PCLK_DIV ) / TICK_PER_SEC )
/****************************************************************************
* Private Types
****************************************************************************/
@ -105,34 +102,37 @@
****************************************************************************/
#ifdef CONFIG_VECTORED_INTERRUPTS
int up_timerisr(uint32_t *regs)
int up_timerisr(uint32_t * regs)
#else
int up_timerisr(int irq, uint32_t *regs)
int up_timerisr(int irq, uint32_t * regs)
#endif
{
static uint32_t tick;
/* Process timer interrupt */
sched_process_timer();
{
static uint32_t tick;
/* Clear the MR0 match interrupt */
/* Process timer interrupt */
tmr_putreg8(TMR_IR_MR0I, TMR_IR_OFFSET);
sched_process_timer();
/* Reset the VIC as well */
/* Clear the MR0 match interrupt */
tmr_putreg8(TMR_IR_MR0I, TMR_IR_OFFSET);
/* Reset the VIC as well */
#ifdef CONFIG_VECTORED_INTERRUPTS
/* write any value to VICAddress to acknowledge the interrupt */
vic_putreg(0, VIC_ADDRESS_OFFSET);
/* write any value to VICAddress to acknowledge the interrupt */
vic_putreg(0, VIC_ADDRESS_OFFSET);
#endif
if(tick++ > 100){
tick =0;
up_statledoff();
}else up_statledon();
return 0;
if (tick++ > 100)
{
tick = 0;
up_statledoff();
}
else
up_statledon();
return 0;
}
/****************************************************************************
@ -149,44 +149,53 @@ void up_timerinit(void)
uint16_t mcr;
/* Power up Timer0 */
SCB_PCONP |= PCTIM0;
/* Timer0 clock input frequency = CCLK / TO_PCLKDIV */
SCB_PCLKSEL0 = (SCB_PCLKSEL0 & ~T0_PCLKSEL_MASK) | TIMER0_PCLKSEL;
/* Clear all match and capture event interrupts */
tmr_putreg8(TMR_IR_ALLI, TMR_IR_OFFSET);
/* Clear the timer counter */
tmr_putreg32(0, TMR_TC_OFFSET);
/* No pre-scaler */
tmr_putreg32(0, TMR_PR_OFFSET);
tmr_putreg32(0, TMR_PC_OFFSET);
/* Set timer match registger to get a TICK_PER_SEC rate
* See arch/board.h and sched/os_internal.h
/* Set timer match register to get a TICK_PER_SEC rate See arch/board.h and
* sched/os_internal.h
*/
tmr_putreg32( T0_TICKS_COUNT, TMR_MR0_OFFSET ); /* 10ms Intterrupt */
tmr_putreg32(T0_TICKS_COUNT, TMR_MR0_OFFSET); /* 10ms Intterrupt */
/* Reset timer counter register and interrupt on match */
mcr = tmr_getreg16(TMR_MCR_OFFSET);
mcr &= ~TMR_MCR_MR1I;
mcr |= (TMR_MCR_MR0I | TMR_MCR_MR0R);
tmr_putreg16(mcr, TMR_MCR_OFFSET);//-- bit 0=1 -int on MR0, bit 1=1 - Reset on MR0
tmr_putreg16(mcr, TMR_MCR_OFFSET); /* -- bit 0=1 -int on MR0, bit 1=1 - Reset on MR0 */
/* Enable counting */
//~ tmr_putreg32(1, TMR_TCR_OFFSET);
/* ~ tmr_putreg32(1, TMR_TCR_OFFSET); */
tmr_putreg8(TMR_CR_ENABLE, TMR_TCR_OFFSET);
/* Attach the timer interrupt vector */
#ifdef CONFIG_VECTORED_INTERRUPTS
up_attach_vector(IRQ_SYSTIMER, PRIORITY_HIGHEST, (vic_vector_t)up_timerisr);
up_attach_vector(IRQ_SYSTIMER, PRIORITY_HIGHEST, (vic_vector_t) up_timerisr);
#else
(void)irq_attach(IRQ_SYSTIMER, (xcpt_t)up_timerisr);
(void)irq_attach(IRQ_SYSTIMER, (xcpt_t) up_timerisr);
up_prioritize_irq(IRQ_SYSTIMER, PRIORITY_HIGHEST);
#endif
/* And enable the system timer interrupt */
up_enable_irq(IRQ_SYSTIMER);