STM32F7 builds broken. This is a work around to at least keep them building.
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@ -60,6 +60,15 @@
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#define HSE_DIVISOR (STM32_HSE_FREQUENCY + 500000) / 1000000
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#define HSE_DIVISOR (STM32_HSE_FREQUENCY + 500000) / 1000000
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/* If CONFIG_STM32F7_DSIHOST is defined in the board configuration, then
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* STM32_RCC_DCKCFGR2_DSISRC must also be defined to selected the clock
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* source.
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*/
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#ifndef STM32_RCC_DCKCFGR2_DSISRC
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# define STM32_RCC_DCKCFGR2_DSISRC RCC_DCKCFGR2_DSISEL_PHY
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#endif
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/* FLASH wait states */
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/* FLASH wait states */
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#if !defined(BOARD_FLASH_WAITSTATES)
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#if !defined(BOARD_FLASH_WAITSTATES)
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