STM32 F7: Add DMA header files
This commit is contained in:
Gregory Nutt
parent
3f1b6ca415
commit
03cbe4ab93
52
arch/arm/src/stm32f7/chip/stm32_dma.h
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52
arch/arm/src/stm32f7/chip/stm32_dma.h
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/************************************************************************************
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* arch/arm/src/stm32f7/chip/stm32_dma.h
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32_DMA_H
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#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32_DMA_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
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# include "chip/stm32f74xx75xx_dma.h"
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#else
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# error "Unsupported STM32 F7 part"
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#endif
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#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_DMA_H */
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551
arch/arm/src/stm32f7/chip/stm32f74xx75xx_dma.h
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551
arch/arm/src/stm32f7/chip/stm32f74xx75xx_dma.h
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/************************************************************************************
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* arch/arm/src/stm32f7/chip/stm32f74xx75xx_dma.h
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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||||
* are met:
|
||||
*
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||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
|
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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||||
*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XXX75XX_DMA_H
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#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XXX75XX_DMA_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* 2 DMA controllers */
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#define DMA1 (0)
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#define DMA2 (1)
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/* 8 DMA streams */
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#define DMA_STREAM0 (0)
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#define DMA_STREAM1 (1)
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#define DMA_STREAM2 (2)
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#define DMA_STREAM3 (3)
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#define DMA_STREAM4 (4)
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#define DMA_STREAM5 (5)
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#define DMA_STREAM6 (6)
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#define DMA_STREAM7 (7)
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/* 8 DMA channels */
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#define DMA_CHAN0 (0)
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#define DMA_CHAN1 (1)
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#define DMA_CHAN2 (2)
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#define DMA_CHAN3 (3)
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#define DMA_CHAN4 (4)
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#define DMA_CHAN5 (5)
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#define DMA_CHAN6 (6)
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#define DMA_CHAN7 (7)
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/* Register Offsets *****************************************************************/
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#define STM32_DMA_LISR_OFFSET 0x0000 /* DMA low interrupt status register */
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#define STM32_DMA_HISR_OFFSET 0x0004 /* DMA high interrupt status register */
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#define STM32_DMA_LIFCR_OFFSET 0x0008 /* DMA low interrupt flag clear register */
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#define STM32_DMA_HIFCR_OFFSET 0x000c /* DMA high interrupt flag clear register */
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#define STM32_DMA_OFFSET(n) (0x0010+0x0018*(n))
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#define STM32_DMA_SCR_OFFSET 0x0000 /* DMA stream n configuration register */
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#define STM32_DMA_SNDTR_OFFSET 0x0004 /* DMA stream n number of data register */
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#define STM32_DMA_SPAR_OFFSET 0x0008 /* DMA stream n peripheral address register */
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#define STM32_DMA_SM0AR_OFFSET 0x000c /* DMA stream n memory 0 address register */
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#define STM32_DMA_SM1AR_OFFSET 0x0010 /* DMA stream n memory 1 address register */
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#define STM32_DMA_SFCR_OFFSET 0x0014 /* DMA stream n FIFO control register */
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#define STM32_DMA_S0CR_OFFSET 0x0010 /* DMA stream 0 configuration register */
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#define STM32_DMA_S1CR_OFFSET 0x0028 /* DMA stream 1 configuration register */
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#define STM32_DMA_S2CR_OFFSET 0x0040 /* DMA stream 2 configuration register */
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#define STM32_DMA_S3CR_OFFSET 0x0058 /* DMA stream 3 configuration register */
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#define STM32_DMA_S4CR_OFFSET 0x0070 /* DMA stream 4 configuration register */
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#define STM32_DMA_S5CR_OFFSET 0x0088 /* DMA stream 5 configuration register */
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#define STM32_DMA_S6CR_OFFSET 0x00a0 /* DMA stream 6 configuration register */
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#define STM32_DMA_S7CR_OFFSET 0x00b8 /* DMA stream 7 configuration register */
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#define STM32_DMA_S0NDTR_OFFSET 0x0014 /* DMA stream 0 number of data register */
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#define STM32_DMA_S1NDTR_OFFSET 0x002c /* DMA stream 1 number of data register */
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#define STM32_DMA_S2NDTR_OFFSET 0x0044 /* DMA stream 2 number of data register */
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#define STM32_DMA_S3NDTR_OFFSET 0x005c /* DMA stream 3 number of data register */
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#define STM32_DMA_S4NDTR_OFFSET 0x0074 /* DMA stream 4 number of data register */
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#define STM32_DMA_S5NDTR_OFFSET 0x008c /* DMA stream 5 number of data register */
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#define STM32_DMA_S6NDTR_OFFSET 0x00a4 /* DMA stream 6 number of data register */
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#define STM32_DMA_S7NDTR_OFFSET 0x00bc /* DMA stream 7 number of data register */
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#define STM32_DMA_S0PAR_OFFSET 0x0018 /* DMA stream 0 peripheral address register */
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#define STM32_DMA_S1PAR_OFFSET 0x0030 /* DMA stream 1 peripheral address register */
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#define STM32_DMA_S2PAR_OFFSET 0x0048 /* DMA stream 2 peripheral address register */
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#define STM32_DMA_S3PAR_OFFSET 0x0060 /* DMA stream 3 peripheral address register */
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#define STM32_DMA_S4PAR_OFFSET 0x0078 /* DMA stream 4 peripheral address register */
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#define STM32_DMA_S5PAR_OFFSET 0x0090 /* DMA stream 5 peripheral address register */
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#define STM32_DMA_S6PAR_OFFSET 0x00a8 /* DMA stream 6 peripheral address register */
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#define STM32_DMA_S7PAR_OFFSET 0x00c0 /* DMA stream 7 peripheral address register */
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#define STM32_DMA_S0M0AR_OFFSET 0x001c /* DMA stream 0 memory 0 address register */
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#define STM32_DMA_S1M0AR_OFFSET 0x0034 /* DMA stream 1 memory 0 address register */
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#define STM32_DMA_S2M0AR_OFFSET 0x004c /* DMA stream 2 memory 0 address register */
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#define STM32_DMA_S3M0AR_OFFSET 0x0064 /* DMA stream 3 memory 0 address register */
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#define STM32_DMA_S4M0AR_OFFSET 0x007c /* DMA stream 4 memory 0 address register */
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#define STM32_DMA_S5M0AR_OFFSET 0x0094 /* DMA stream 5 memory 0 address register */
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#define STM32_DMA_S6M0AR_OFFSET 0x00ac /* DMA stream 6 memory 0 address register */
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#define STM32_DMA_S7M0AR_OFFSET 0x00c4 /* DMA stream 7 memory 0 address register */
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#define STM32_DMA_S0M1AR_OFFSET 0x0020 /* DMA stream 0 memory 1 address register */
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#define STM32_DMA_S1M1AR_OFFSET 0x0038 /* DMA stream 1 memory 1 address register */
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#define STM32_DMA_S2M1AR_OFFSET 0x0050 /* DMA stream 2 memory 1 address register */
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#define STM32_DMA_S3M1AR_OFFSET 0x0068 /* DMA stream 3 memory 1 address register */
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#define STM32_DMA_S4M1AR_OFFSET 0x0080 /* DMA stream 4 memory 1 address register */
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#define STM32_DMA_S5M1AR_OFFSET 0x0098 /* DMA stream 5 memory 1 address register */
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#define STM32_DMA_S6M1AR_OFFSET 0x00b0 /* DMA stream 6 memory 1 address register */
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#define STM32_DMA_S7M1AR_OFFSET 0x00c8 /* DMA stream 7 memory 1 address register */
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#define STM32_DMA_S0FCR_OFFSET 0x0024 /* DMA stream 0 FIFO control register */
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#define STM32_DMA_S1FCR_OFFSET 0x003c /* DMA stream 1 FIFO control register */
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#define STM32_DMA_S2FCR_OFFSET 0x0054 /* DMA stream 2 FIFO control register */
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#define STM32_DMA_S3FCR_OFFSET 0x006c /* DMA stream 3 FIFO control register */
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#define STM32_DMA_S4FCR_OFFSET 0x0084 /* DMA stream 4 FIFO control register */
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#define STM32_DMA_S5FCR_OFFSET 0x009c /* DMA stream 5 FIFO control register */
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#define STM32_DMA_S6FCR_OFFSET 0x00b4 /* DMA stream 6 FIFO control register */
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#define STM32_DMA_S7FCR_OFFSET 0x00cc /* DMA stream 7 FIFO control register */
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/* Register Addresses ***************************************************************/
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#define STM32_DMA1_LISRC (STM32_DMA1_BASE+STM32_DMA_LISR_OFFSET)
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#define STM32_DMA1_HISRC (STM32_DMA1_BASE+STM32_DMA_HISR_OFFSET)
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#define STM32_DMA1_LIFCR (STM32_DMA1_BASE+STM32_DMA_LIFCR_OFFSET)
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#define STM32_DMA1_HIFCR (STM32_DMA1_BASE+STM32_DMA_HIFCR_OFFSET)
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#define STM32_DMA1_SCR(n) (STM32_DMA1_BASE+STM32_DMA_SCR_OFFSET+STM32_DMA_OFFSET(n))
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#define STM32_DMA1_S0CR (STM32_DMA1_BASE+STM32_DMA_S0CR_OFFSET)
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#define STM32_DMA1_S1CR (STM32_DMA1_BASE+STM32_DMA_S1CR_OFFSET)
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#define STM32_DMA1_S2CR (STM32_DMA1_BASE+STM32_DMA_S2CR_OFFSET)
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#define STM32_DMA1_S3CR (STM32_DMA1_BASE+STM32_DMA_S3CR_OFFSET)
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#define STM32_DMA1_S4CR (STM32_DMA1_BASE+STM32_DMA_S4CR_OFFSET)
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#define STM32_DMA1_S5CR (STM32_DMA1_BASE+STM32_DMA_S5CR_OFFSET)
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#define STM32_DMA1_S6CR (STM32_DMA1_BASE+STM32_DMA_S6CR_OFFSET)
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#define STM32_DMA1_S7CR (STM32_DMA1_BASE+STM32_DMA_S7CR_OFFSET)
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#define STM32_DMA1_SNDTR(n) (STM32_DMA1_BASE+STM32_DMA_SNDTR_OFFSET+STM32_DMA_OFFSET(n))
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#define STM32_DMA1_S0NDTR (STM32_DMA1_BASE+STM32_DMA_S0NDTR_OFFSET)
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#define STM32_DMA1_S1NDTR (STM32_DMA1_BASE+STM32_DMA_S1NDTR_OFFSET)
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#define STM32_DMA1_S2NDTR (STM32_DMA1_BASE+STM32_DMA_S2NDTR_OFFSET)
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#define STM32_DMA1_S3NDTR (STM32_DMA1_BASE+STM32_DMA_S3NDTR_OFFSET)
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#define STM32_DMA1_S4NDTR (STM32_DMA1_BASE+STM32_DMA_S4NDTR_OFFSET)
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#define STM32_DMA1_S5NDTR (STM32_DMA1_BASE+STM32_DMA_S5NDTR_OFFSET)
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#define STM32_DMA1_S6NDTR (STM32_DMA1_BASE+STM32_DMA_S6NDTR_OFFSET)
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#define STM32_DMA1_S7NDTR (STM32_DMA1_BASE+STM32_DMA_S7NDTR_OFFSET)
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#define STM32_DMA1_SPAR(n) (STM32_DMA1_BASE+STM32_DMA_SPAR_OFFSET+STM32_DMA_OFFSET(n))
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#define STM32_DMA1_S0PAR (STM32_DMA1_BASE+STM32_DMA_S0PAR_OFFSET)
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#define STM32_DMA1_S1PAR (STM32_DMA1_BASE+STM32_DMA_S1PAR_OFFSET)
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#define STM32_DMA1_S2PAR (STM32_DMA1_BASE+STM32_DMA_S2PAR_OFFSET)
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#define STM32_DMA1_S3PAR (STM32_DMA1_BASE+STM32_DMA_S3PAR_OFFSET)
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#define STM32_DMA1_S4PAR (STM32_DMA1_BASE+STM32_DMA_S4PAR_OFFSET)
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#define STM32_DMA1_S5PAR (STM32_DMA1_BASE+STM32_DMA_S5PAR_OFFSET)
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#define STM32_DMA1_S6PAR (STM32_DMA1_BASE+STM32_DMA_S6PAR_OFFSET)
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#define STM32_DMA1_S7PAR (STM32_DMA1_BASE+STM32_DMA_S7PAR_OFFSET)
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#define STM32_DMA1_SM0AR(n) (STM32_DMA1_BASE+STM32_DMA_SM0AR_OFFSET+STM32_DMA_OFFSET(n))
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#define STM32_DMA1_S0M0AR (STM32_DMA1_BASE+STM32_DMA_S0M0AR_OFFSET)
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#define STM32_DMA1_S1M0AR (STM32_DMA1_BASE+STM32_DMA_S1M0AR_OFFSET)
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#define STM32_DMA1_S2M0AR (STM32_DMA1_BASE+STM32_DMA_S2M0AR_OFFSET)
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#define STM32_DMA1_S3M0AR (STM32_DMA1_BASE+STM32_DMA_S3M0AR_OFFSET)
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#define STM32_DMA1_S4M0AR (STM32_DMA1_BASE+STM32_DMA_S4M0AR_OFFSET)
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#define STM32_DMA1_S5M0AR (STM32_DMA1_BASE+STM32_DMA_S5M0AR_OFFSET)
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#define STM32_DMA1_S6M0AR (STM32_DMA1_BASE+STM32_DMA_S6M0AR_OFFSET)
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#define STM32_DMA1_S7M0AR (STM32_DMA1_BASE+STM32_DMA_S7M0AR_OFFSET)
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#define STM32_DMA1_SM1AR(n) (STM32_DMA1_BASE+STM32_DMA_SM1AR_OFFSET+STM32_DMA_OFFSET(n))
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#define STM32_DMA1_S0M1AR (STM32_DMA1_BASE+STM32_DMA_S0M1AR_OFFSET)
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#define STM32_DMA1_S1M1AR (STM32_DMA1_BASE+STM32_DMA_S1M1AR_OFFSET)
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#define STM32_DMA1_S2M1AR (STM32_DMA1_BASE+STM32_DMA_S2M1AR_OFFSET)
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#define STM32_DMA1_S3M1AR (STM32_DMA1_BASE+STM32_DMA_S3M1AR_OFFSET)
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#define STM32_DMA1_S4M1AR (STM32_DMA1_BASE+STM32_DMA_S4M1AR_OFFSET)
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#define STM32_DMA1_S5M1AR (STM32_DMA1_BASE+STM32_DMA_S5M1AR_OFFSET)
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#define STM32_DMA1_S6M1AR (STM32_DMA1_BASE+STM32_DMA_S6M1AR_OFFSET)
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#define STM32_DMA1_S7M1AR (STM32_DMA1_BASE+STM32_DMA_S7M1AR_OFFSET)
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#define STM32_DMA1_SFCR(n) (STM32_DMA1_BASE+STM32_DMA_SFCR_OFFSET+STM32_DMA_OFFSET(n))
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#define STM32_DMA1_S0FCR (STM32_DMA1_BASE+STM32_DMA_S0FCR_OFFSET)
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#define STM32_DMA1_S1FCR (STM32_DMA1_BASE+STM32_DMA_S1FCR_OFFSET)
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#define STM32_DMA1_S2FCR (STM32_DMA1_BASE+STM32_DMA_S2FCR_OFFSET)
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#define STM32_DMA1_S3FCR (STM32_DMA1_BASE+STM32_DMA_S3FCR_OFFSET)
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#define STM32_DMA1_S4FCR (STM32_DMA1_BASE+STM32_DMA_S4FCR_OFFSET)
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#define STM32_DMA1_S5FCR (STM32_DMA1_BASE+STM32_DMA_S5FCR_OFFSET)
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#define STM32_DMA1_S6FCR (STM32_DMA1_BASE+STM32_DMA_S6FCR_OFFSET)
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#define STM32_DMA1_S7FCR (STM32_DMA1_BASE+STM32_DMA_S7FCR_OFFSET)
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#define STM32_DMA2_LISRC (STM32_DMA2_BASE+STM32_DMA_LISR_OFFSET)
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#define STM32_DMA2_HISRC (STM32_DMA2_BASE+STM32_DMA_HISR_OFFSET)
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#define STM32_DMA2_LIFCR (STM32_DMA2_BASE+STM32_DMA_LIFCR_OFFSET)
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#define STM32_DMA2_HIFCR (STM32_DMA2_BASE+STM32_DMA_HIFCR_OFFSET)
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#define STM32_DMA2_SCR(n) (STM32_DMA2_BASE+STM32_DMA_SCR_OFFSET+STM32_DMA_OFFSET(n))
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#define STM32_DMA2_S0CR (STM32_DMA2_BASE+STM32_DMA_S0CR_OFFSET)
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#define STM32_DMA2_S1CR (STM32_DMA2_BASE+STM32_DMA_S1CR_OFFSET)
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#define STM32_DMA2_S2CR (STM32_DMA2_BASE+STM32_DMA_S2CR_OFFSET)
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#define STM32_DMA2_S3CR (STM32_DMA2_BASE+STM32_DMA_S3CR_OFFSET)
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#define STM32_DMA2_S4CR (STM32_DMA2_BASE+STM32_DMA_S4CR_OFFSET)
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#define STM32_DMA2_S5CR (STM32_DMA2_BASE+STM32_DMA_S5CR_OFFSET)
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#define STM32_DMA2_S6CR (STM32_DMA2_BASE+STM32_DMA_S6CR_OFFSET)
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#define STM32_DMA2_S7CR (STM32_DMA2_BASE+STM32_DMA_S7CR_OFFSET)
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#define STM32_DMA2_SNDTR(n) (STM32_DMA2_BASE+STM32_DMA_SNDTR_OFFSET+STM32_DMA_OFFSET(n))
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#define STM32_DMA2_S0NDTR (STM32_DMA2_BASE+STM32_DMA_S0NDTR_OFFSET)
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#define STM32_DMA2_S1NDTR (STM32_DMA2_BASE+STM32_DMA_S1NDTR_OFFSET)
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#define STM32_DMA2_S2NDTR (STM32_DMA2_BASE+STM32_DMA_S2NDTR_OFFSET)
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#define STM32_DMA2_S3NDTR (STM32_DMA2_BASE+STM32_DMA_S3NDTR_OFFSET)
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#define STM32_DMA2_S4NDTR (STM32_DMA2_BASE+STM32_DMA_S4NDTR_OFFSET)
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#define STM32_DMA2_S5NDTR (STM32_DMA2_BASE+STM32_DMA_S5NDTR_OFFSET)
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#define STM32_DMA2_S6NDTR (STM32_DMA2_BASE+STM32_DMA_S6NDTR_OFFSET)
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#define STM32_DMA2_S7NDTR (STM32_DMA2_BASE+STM32_DMA_S7NDTR_OFFSET)
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#define STM32_DMA2_SPAR(n) (STM32_DMA2_BASE+STM32_DMA_SPAR_OFFSET+STM32_DMA_OFFSET(n))
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||||
#define STM32_DMA2_S0PAR (STM32_DMA2_BASE+STM32_DMA_S0PAR_OFFSET)
|
||||
#define STM32_DMA2_S1PAR (STM32_DMA2_BASE+STM32_DMA_S1PAR_OFFSET)
|
||||
#define STM32_DMA2_S2PAR (STM32_DMA2_BASE+STM32_DMA_S2PAR_OFFSET)
|
||||
#define STM32_DMA2_S3PAR (STM32_DMA2_BASE+STM32_DMA_S3PAR_OFFSET)
|
||||
#define STM32_DMA2_S4PAR (STM32_DMA2_BASE+STM32_DMA_S4PAR_OFFSET)
|
||||
#define STM32_DMA2_S5PAR (STM32_DMA2_BASE+STM32_DMA_S5PAR_OFFSET)
|
||||
#define STM32_DMA2_S6PAR (STM32_DMA2_BASE+STM32_DMA_S6PAR_OFFSET)
|
||||
#define STM32_DMA2_S7PAR (STM32_DMA2_BASE+STM32_DMA_S7PAR_OFFSET)
|
||||
|
||||
#define STM32_DMA2_SM0AR(n) (STM32_DMA2_BASE+STM32_DMA_SM0AR_OFFSET+STM32_DMA_OFFSET(n))
|
||||
#define STM32_DMA2_S0M0AR (STM32_DMA2_BASE+STM32_DMA_S0M0AR_OFFSET)
|
||||
#define STM32_DMA2_S1M0AR (STM32_DMA2_BASE+STM32_DMA_S1M0AR_OFFSET)
|
||||
#define STM32_DMA2_S2M0AR (STM32_DMA2_BASE+STM32_DMA_S2M0AR_OFFSET)
|
||||
#define STM32_DMA2_S3M0AR (STM32_DMA2_BASE+STM32_DMA_S3M0AR_OFFSET)
|
||||
#define STM32_DMA2_S4M0AR (STM32_DMA2_BASE+STM32_DMA_S4M0AR_OFFSET)
|
||||
#define STM32_DMA2_S5M0AR (STM32_DMA2_BASE+STM32_DMA_S5M0AR_OFFSET)
|
||||
#define STM32_DMA2_S6M0AR (STM32_DMA2_BASE+STM32_DMA_S6M0AR_OFFSET)
|
||||
#define STM32_DMA2_S7M0AR (STM32_DMA2_BASE+STM32_DMA_S7M0AR_OFFSET)
|
||||
|
||||
#define STM32_DMA2_SM1AR(n) (STM32_DMA2_BASE+STM32_DMA_SM1AR_OFFSET+STM32_DMA_OFFSET(n))
|
||||
#define STM32_DMA2_S0M1AR (STM32_DMA2_BASE+STM32_DMA_S0M1AR_OFFSET)
|
||||
#define STM32_DMA2_S1M1AR (STM32_DMA2_BASE+STM32_DMA_S1M1AR_OFFSET)
|
||||
#define STM32_DMA2_S2M1AR (STM32_DMA2_BASE+STM32_DMA_S2M1AR_OFFSET)
|
||||
#define STM32_DMA2_S3M1AR (STM32_DMA2_BASE+STM32_DMA_S3M1AR_OFFSET)
|
||||
#define STM32_DMA2_S4M1AR (STM32_DMA2_BASE+STM32_DMA_S4M1AR_OFFSET)
|
||||
#define STM32_DMA2_S5M1AR (STM32_DMA2_BASE+STM32_DMA_S5M1AR_OFFSET)
|
||||
#define STM32_DMA2_S6M1AR (STM32_DMA2_BASE+STM32_DMA_S6M1AR_OFFSET)
|
||||
#define STM32_DMA2_S7M1AR (STM32_DMA2_BASE+STM32_DMA_S7M1AR_OFFSET)
|
||||
|
||||
#define STM32_DMA2_SFCR(n) (STM32_DMA2_BASE+STM32_DMA_SFCR_OFFSET+STM32_DMA_OFFSET(n))
|
||||
#define STM32_DMA2_S0FCR (STM32_DMA2_BASE+STM32_DMA_S0FCR_OFFSET)
|
||||
#define STM32_DMA2_S1FCR (STM32_DMA2_BASE+STM32_DMA_S1FCR_OFFSET)
|
||||
#define STM32_DMA2_S2FCR (STM32_DMA2_BASE+STM32_DMA_S2FCR_OFFSET)
|
||||
#define STM32_DMA2_S3FCR (STM32_DMA2_BASE+STM32_DMA_S3FCR_OFFSET)
|
||||
#define STM32_DMA2_S4FCR (STM32_DMA2_BASE+STM32_DMA_S4FCR_OFFSET)
|
||||
#define STM32_DMA2_S5FCR (STM32_DMA2_BASE+STM32_DMA_S5FCR_OFFSET)
|
||||
#define STM32_DMA2_S6FCR (STM32_DMA2_BASE+STM32_DMA_S6FCR_OFFSET)
|
||||
#define STM32_DMA2_S7FCR (STM32_DMA2_BASE+STM32_DMA_S7FCR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
|
||||
#define DMA_STREAM_MASK 0x3f
|
||||
#define DMA_STREAM_FEIF_BIT (1 << 0) /* Bit 0: Stream FIFO error interrupt flag */
|
||||
#define DMA_STREAM_DMEIF_BIT (1 << 2) /* Bit 2: Stream direct mode error interrupt flag */
|
||||
#define DMA_STREAM_TEIF_BIT (1 << 3) /* Bit 3: Stream Transfer Error flag */
|
||||
#define DMA_STREAM_HTIF_BIT (1 << 4) /* Bit 4: Stream Half Transfer flag */
|
||||
#define DMA_STREAM_TCIF_BIT (1 << 5) /* Bit 5: Stream Transfer Complete flag */
|
||||
|
||||
/* DMA interrupt status register and interrupt flag clear register field definitions */
|
||||
|
||||
#define DMA_INT_STREAM0_SHIFT (0) /* Bits 0-5: DMA Stream 0 interrupt */
|
||||
#define DMA_INT_STREAM0_MASK (DMA_STREAM_MASK << DMA_INT_STREAM0_SHIFT)
|
||||
#define DMA_INT_STREAM1_SHIFT (6) /* Bits 6-11: DMA Stream 1 interrupt */
|
||||
#define DMA_INT_STREAM1_MASK (DMA_STREAM_MASK << DMA_INT_STREAM1_SHIFT)
|
||||
#define DMA_INT_STREAM2_SHIFT (16) /* Bits 16-21: DMA Stream 2 interrupt */
|
||||
#define DMA_INT_STREAM2_MASK (DMA_STREAM_MASK << DMA_INT_STREAM2_SHIFT)
|
||||
#define DMA_INT_STREAM3_SHIFT (22) /* Bits 22-27: DMA Stream 3 interrupt */
|
||||
#define DMA_INT_STREAM3_MASK (DMA_STREAM_MASK << DMA_INT_STREAM3_SHIFT)
|
||||
|
||||
#define DMA_INT_STREAM4_SHIFT (0) /* Bits 0-5: DMA Stream 4 interrupt */
|
||||
#define DMA_INT_STREAM4_MASK (DMA_STREAM_MASK << DMA_INT_STREAM4_SHIFT)
|
||||
#define DMA_INT_STREAM5_SHIFT (6) /* Bits 6-11: DMA Stream 5 interrupt */
|
||||
#define DMA_INT_STREAM5_MASK (DMA_STREAM_MASK << DMA_INT_STREAM5_SHIFT)
|
||||
#define DMA_INT_STREAM6_SHIFT (16) /* Bits 16-21: DMA Stream 6 interrupt */
|
||||
#define DMA_INT_STREAM6_MASK (DMA_STREAM_MASK << DMA_INT_STREAM6_SHIFT)
|
||||
#define DMA_INT_STREAM7_SHIFT (22) /* Bits 22-27: DMA Stream 7 interrupt */
|
||||
#define DMA_INT_STREAM7_MASK (DMA_STREAM_MASK << DMA_INT_STREAM7_SHIFT)
|
||||
|
||||
/* DMA stream configuration register */
|
||||
|
||||
#define DMA_SCR_EN (1 << 0) /* Bit 0: Stream enable */
|
||||
#define DMA_SCR_DMEIE (1 << 1) /* Bit 1: Direct mode error interrupt enable */
|
||||
#define DMA_SCR_TEIE (1 << 2) /* Bit 2: Transfer error interrupt enable */
|
||||
#define DMA_SCR_HTIE (1 << 3) /* Bit 3: Half Transfer interrupt enable */
|
||||
#define DMA_SCR_TCIE (1 << 4) /* Bit 4: Transfer complete interrupt enable */
|
||||
#define DMA_SCR_PFCTRL (1 << 5) /* Bit 5: Peripheral flow controller */
|
||||
#define DMA_SCR_DIR_SHIFT (6) /* Bits 6-7: Data transfer direction */
|
||||
#define DMA_SCR_DIR_MASK (3 << DMA_SCR_DIR_SHIFT)
|
||||
# define DMA_SCR_DIR_P2M (0 << DMA_SCR_DIR_SHIFT) /* 00: Peripheral-to-memory */
|
||||
# define DMA_SCR_DIR_M2P (1 << DMA_SCR_DIR_SHIFT) /* 01: Memory-to-peripheral */
|
||||
# define DMA_SCR_DIR_M2M (2 << DMA_SCR_DIR_SHIFT) /* 10: Memory-to-memory */
|
||||
#define DMA_SCR_CIRC (1 << 8) /* Bit 8: Circular mode */
|
||||
#define DMA_SCR_PINC (1 << 9) /* Bit 9: Peripheral increment mode */
|
||||
#define DMA_SCR_MINC (1 << 10) /* Bit 10: Memory increment mode */
|
||||
#define DMA_SCR_PSIZE_SHIFT (11) /* Bits 11-12: Peripheral size */
|
||||
#define DMA_SCR_PSIZE_MASK (3 << DMA_SCR_PSIZE_SHIFT)
|
||||
# define DMA_SCR_PSIZE_8BITS (0 << DMA_SCR_PSIZE_SHIFT) /* 00: 8-bits */
|
||||
# define DMA_SCR_PSIZE_16BITS (1 << DMA_SCR_PSIZE_SHIFT) /* 01: 16-bits */
|
||||
# define DMA_SCR_PSIZE_32BITS (2 << DMA_SCR_PSIZE_SHIFT) /* 10: 32-bits */
|
||||
#define DMA_SCR_MSIZE_SHIFT (13) /* Bits 13-14: Memory size */
|
||||
#define DMA_SCR_MSIZE_MASK (3 << DMA_SCR_MSIZE_SHIFT)
|
||||
# define DMA_SCR_MSIZE_8BITS (0 << DMA_SCR_MSIZE_SHIFT) /* 00: 8-bits */
|
||||
# define DMA_SCR_MSIZE_16BITS (1 << DMA_SCR_MSIZE_SHIFT) /* 01: 16-bits */
|
||||
# define DMA_SCR_MSIZE_32BITS (2 << DMA_SCR_MSIZE_SHIFT) /* 10: 32-bits */
|
||||
#define DMA_SCR_PINCOS (1 << 15) /* Bit 15: Peripheral increment offset size */
|
||||
#define DMA_SCR_PL_SHIFT (16) /* Bits 16-17: Stream Priority level */
|
||||
#define DMA_SCR_PL_MASK (3 << DMA_SCR_PL_SHIFT)
|
||||
# define DMA_SCR_PRILO (0 << DMA_SCR_PL_SHIFT) /* 00: Low */
|
||||
# define DMA_SCR_PRIMED (1 << DMA_SCR_PL_SHIFT) /* 01: Medium */
|
||||
# define DMA_SCR_PRIHI (2 << DMA_SCR_PL_SHIFT) /* 10: High */
|
||||
# define DMA_SCR_PRIVERYHI (3 << DMA_SCR_PL_SHIFT) /* 11: Very high */
|
||||
#define DMA_SCR_DBM (1 << 18) /* Bit 15: Double buffer mode */
|
||||
#define DMA_SCR_CT (1 << 19) /* Bit 19: Current target */
|
||||
#define DMA_SCR_PBURST_SHIFT (21) /* Bits 21-22: Peripheral burst transfer configuration */
|
||||
#define DMA_SCR_PBURST_MASK (3 << DMA_SCR_PBURST_SHIFT)
|
||||
# define DMA_SCR_PBURST_SINGLE (0 << DMA_SCR_PBURST_SHIFT) /* 00: Single transfer */
|
||||
# define DMA_SCR_PBURST_INCR4 (1 << DMA_SCR_PBURST_SHIFT) /* 01: Incremental burst of 4 beats */
|
||||
# define DMA_SCR_PBURST_INCR8 (2 << DMA_SCR_PBURST_SHIFT) /* 10: Incremental burst of 8 beats */
|
||||
# define DMA_SCR_PBURST_INCR16 (3 << DMA_SCR_PBURST_SHIFT) /* 11: Incremental burst of 16 beats */
|
||||
#define DMA_SCR_MBURST_SHIFT (23) /* Bits 23-24: Memory burst transfer configuration */
|
||||
#define DMA_SCR_MBURST_MASK (3 << DMA_SCR_MBURST_SHIFT)
|
||||
# define DMA_SCR_MBURST_SINGLE (0 << DMA_SCR_MBURST_SHIFT) /* 00: Single transfer */
|
||||
# define DMA_SCR_MBURST_INCR4 (1 << DMA_SCR_MBURST_SHIFT) /* 01: Incremental burst of 4 beats */
|
||||
# define DMA_SCR_MBURST_INCR8 (2 << DMA_SCR_MBURST_SHIFT) /* 10: Incremental burst of 8 beats */
|
||||
# define DMA_SCR_MBURST_INCR16 (3 << DMA_SCR_MBURST_SHIFT) /* 11: Incremental burst of 16 beats */
|
||||
#define DMA_SCR_CHSEL_SHIFT (25) /* Bits 25-27: Channel selection */
|
||||
#define DMA_SCR_CHSEL_MASK (7 << DMA_SCR_CHSEL_SHIFT)
|
||||
# define DMA_SCR_CHSEL(n) ((n) << DMA_SCR_CHSEL_SHIFT)
|
||||
|
||||
#define DMA_SCR_ALLINTS (DMA_SCR_DMEIE|DMA_SCR_TEIE|DMA_SCR_HTIE|DMA_SCR_TCIE)
|
||||
|
||||
/* DMA stream number of data register */
|
||||
|
||||
#define DMA_SNDTR_NDT_SHIFT (0) /* Bits 15-0: Number of data to Transfer */
|
||||
#define DMA_SNDTR_NDT_MASK (0xffff << DMA_SNDTR_NDT_SHIFT)
|
||||
|
||||
/* DMA stream n FIFO control register */
|
||||
|
||||
#define DMA_SFCR_FTH_SHIFT (0) /* Bits 0-1: FIFO threshold selection */
|
||||
#define DMA_SFCR_FTH_MASK (3 << DMA_SFCR_FTH_SHIFT)
|
||||
# define DMA_SFCR_FTH_QUARTER (0 << DMA_SFCR_FTH_SHIFT) /* 1/4 full FIFO */
|
||||
# define DMA_SFCR_FTH_HALF (1 << DMA_SFCR_FTH_SHIFT) /* 1/2 full FIFO */
|
||||
# define DMA_SFCR_FTH_3QUARTER (2 << DMA_SFCR_FTH_SHIFT) /* 3/4 full FIFO */
|
||||
# define DMA_SFCR_FTH_FULL (3 << DMA_SFCR_FTH_SHIFT) /* full FIFO */
|
||||
#define DMA_SFCR_DMDIS (1 << 2) /* Bit 2: Direct mode disable */
|
||||
#define DMA_SFCR_FS_SHIFT (3) /* Bits 3-5: FIFO status */
|
||||
#define DMA_SFCR_FS_MASK (7 << DMA_SFCR_FS_SHIFT)
|
||||
# define DMA_SFCR_FS_QUARTER (0 << DMA_SFCR_FS_SHIFT) /* 0 < fifo_level < 1/4 */
|
||||
# define DMA_SFCR_FS_HALF (1 << DMA_SFCR_FS_SHIFT) /* 1/4 = fifo_level < 1/2 */
|
||||
# define DMA_SFCR_FS_3QUARTER (2 << DMA_SFCR_FS_SHIFT) /* 1/2 = fifo_level < 3/4 */
|
||||
# define DMA_SFCR_FS_ALMOSTFULL (3 << DMA_SFCR_FS_SHIFT) /* 3/4 = fifo_level < full */
|
||||
# define DMA_SFCR_FS_EMPTY (4 << DMA_SFCR_FS_SHIFT) /* FIFO is empty */
|
||||
# define DMA_SFCR_FS_FULL (5 << DMA_SFCR_FS_SHIFT) /* FIFO is full */
|
||||
/* Bit 6: Reserved */
|
||||
#define DMA_SFCR_FEIE (1 << 7) /* Bit 7: FIFO error interrupt enable */
|
||||
/* Bits 8-31: Reserved */
|
||||
|
||||
/* DMA Stream mapping. Each DMA stream has a mapping to several possible
|
||||
* sources/sinks of data. The requests from peripherals assigned to a stream
|
||||
* are simply OR'ed together before entering the DMA block. This means that only
|
||||
* one request on a given stream can be enabled at once.
|
||||
*
|
||||
* Alternative stream selections are provided with a numeric suffix like _1, _2, etc.
|
||||
* The DMA driver, however, will use the pin selection without the numeric suffix.
|
||||
* Additional definitions are required in the board.h file. For example, if
|
||||
* SPI3_RX connects via DMA STREAM0, then following should be application-specific
|
||||
* mapping should be used:
|
||||
*
|
||||
* #define DMAMAP_SPI3_RX DMAMAP_SPI3_RX_1
|
||||
*/
|
||||
|
||||
#define STM32_DMA_MAP(d,s,c) ((d) << 6 | (s) << 3 | (c))
|
||||
#define STM32_DMA_CONTROLLER(m) (((m) >> 6) & 1)
|
||||
#define STM32_DMA_STREAM(m) (((m) >> 3) & 7)
|
||||
#define STM32_DMA_CHANNEL(m) ((m) & 7)
|
||||
|
||||
#define DMAMAP_SPI3_RX_1 STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN0)
|
||||
#define DMAMAP_SPDIFRX_DT STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN0)
|
||||
#define DMAMAP_SPI3_RX_2 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN0)
|
||||
#define DMAMAP_SPI2_RX STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN0)
|
||||
#define DMAMAP_SPI2_TX STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN0)
|
||||
#define DMAMAP_SPI3_TX_1 STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN0)
|
||||
#define DMAMAP_SPDIFRX_CS STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN0)
|
||||
#define DMAMAP_SPI3_TX_2 STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN0)
|
||||
|
||||
#define DMAMAP_I2C1_RX_1 STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN1)
|
||||
#define DMAMAP_I2C3_RX STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN1)
|
||||
#define DMAMAP_TIM7_UP_1 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN1)
|
||||
#define DMAMAP_TIM7_UP_2 STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN1)
|
||||
#define DMAMAP_I2C1_RX_2 STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN1)
|
||||
#define DMAMAP_I2C1_TX_1 STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN1)
|
||||
#define DMAMAP_I2C1_TX_2 STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN1)
|
||||
|
||||
#define DMAMAP_TIM4_CH1 STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN2)
|
||||
#define DMAMAP_I2C_RX STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN2)
|
||||
#define DMAMAP_TIM4_CH2 STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN2)
|
||||
#define DMAMAP_I2C4_TX STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN2)
|
||||
#define DMAMAP_TIM4_UP STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN2)
|
||||
#define DMAMAP_TIM4_CH3 STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN2)
|
||||
|
||||
#define DMAMAP_TIM2_UP_1 STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN3)
|
||||
#define DMAMAP_TIM2_CH3 STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN3)
|
||||
#define DMAMAP_I2C3_RX STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN3)
|
||||
#define DMAMAP_I2C3_TX STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN3)
|
||||
#define DMAMAP_TIM2_CH1 STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN3)
|
||||
#define DMAMAP_TIM2_CH2 STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN3)
|
||||
#define DMAMAP_TIM2_CH4_1 STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN3)
|
||||
#define DMAMAP_TIM2_UP_2 STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN3)
|
||||
#define DMAMAP_TIM2_CH4_2 STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN3)
|
||||
|
||||
#define DMAMAP_UART5_RX STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN4)
|
||||
#define DMAMAP_USART3_RX STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN4)
|
||||
#define DMAMAP_UART4_RX STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN4)
|
||||
#define DMAMAP_USART3_TX_1 STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN4)
|
||||
#define DMAMAP_UART4_TX STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN4)
|
||||
#define DMAMAP_USART2_RX STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN4)
|
||||
#define DMAMAP_USART2_TX STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN4)
|
||||
#define DMAMAP_UART5_TX STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN4)
|
||||
|
||||
#define DMAMAP_UART8_TX STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN5)
|
||||
#define DMAMAP_UART7_TX STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN5)
|
||||
#define DMAMAP_TIM3_CH4 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN5)
|
||||
#define DMAMAP_TIM3_UP STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN5)
|
||||
#define DMAMAP_UART7_RX STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN5)
|
||||
#define DMAMAP_TIM3_CH1 STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN5)
|
||||
#define DMAMAP_TIM3_TRIG STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN5)
|
||||
#define DMAMAP_TIM3_CH2 STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN5)
|
||||
#define DMAMAP_UART8_RX STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN5)
|
||||
#define DMAMAP_TIM3_CH3 STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN5)
|
||||
|
||||
#define DMAMAP_TIM5_CH3 STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN6)
|
||||
#define DMAMAP_TIM5_UP_1 STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN6)
|
||||
#define DMAMAP_TIM5_CH4_1 STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN6)
|
||||
#define DMAMAP_TIM5_TRIG_1 STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN6)
|
||||
#define DMAMAP_TIM5_CH1 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN6)
|
||||
#define DMAMAP_TIM5_CH4_2 STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN6)
|
||||
#define DMAMAP_TIM5_TRIG_2 STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN6)
|
||||
#define DMAMAP_TIM5_CH2 STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN6)
|
||||
#define DMAMAP_TIM5_UP_2 STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN6)
|
||||
|
||||
#define DMAMAP_TIM6_UP STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN7)
|
||||
#define DMAMAP_I2C2_RX_1 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN7)
|
||||
#define DMAMAP_I2C2_RX_2 STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN7)
|
||||
#define DMAMAP_USART3_TX_2 STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN7)
|
||||
#define DMAMAP_DAC1 STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN7)
|
||||
#define DMAMAP_DAC2 STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN7)
|
||||
#define DMAMAP_I2C2_TX STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN7)
|
||||
|
||||
#define DMAMAP_ADC1_1 STM32_DMA_MAP(DMA2,DMA_STREAM0,DMA_CHAN0)
|
||||
#define DMAMAP_SAI1_A_1 STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN0)
|
||||
#define DMAMAP_TIM8_CH1_1 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN0)
|
||||
#define DMAMAP_TIM8_CH2_1 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN0)
|
||||
#define DMAMAP_TIM8_CH3_1 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN0)
|
||||
#define DMAMAP_SAI1_A_2 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN0)
|
||||
#define DMAMAP_ADC1_2 STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN0)
|
||||
#define DMAMAP_SAI1_B_1 STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN0)
|
||||
#define DMAMAP_TIM1_CH1_1 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN0)
|
||||
#define DMAMAP_TIM1_CH2_1 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN0)
|
||||
#define DMAMAP_TIM1_CH3_1 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN0)
|
||||
#define DMAMAP_SAI1_B_2 STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN0)
|
||||
|
||||
#define DMAMAP_DCMI_1 STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN1)
|
||||
#define DMAMAP_ADC2_1 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN1)
|
||||
#define DMAMAP_ADC2_2 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN1)
|
||||
#define DMAMAP_SAI1_B STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN1)
|
||||
#define DMAMAP_SPI6_TX STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN1)
|
||||
#define DMAMAP_SPI6_RX STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN1)
|
||||
#define DMAMAP_DCMI_2 STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN1)
|
||||
|
||||
#define DMAMAP_ADC3_1 STM32_DMA_MAP(DMA2,DMA_STREAM0,DMA_CHAN2)
|
||||
#define DMAMAP_ADC3_2 STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN2)
|
||||
#define DMAMAP_SPI5_RX_1 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN2)
|
||||
#define DMAMAP_SPI5_TX_1 STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN2)
|
||||
#define DMAMAP_CRYP_OUT STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN2)
|
||||
#define DMAMAP_CRYP_IN STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN2)
|
||||
#define DMAMAP_HASH_IN STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN2)
|
||||
|
||||
#define DMAMAP_SPI1_RX_1 STM32_DMA_MAP(DMA2,DMA_STREAM0,DMA_CHAN3)
|
||||
#define DMAMAP_SPI1_RX_2 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN3)
|
||||
#define DMAMAP_SPI1_TX_1 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN3)
|
||||
#define DMAMAP_SAI2_A STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN3)
|
||||
#define DMAMAP_SPI1_TX_2 STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN3)
|
||||
#define DMAMAP_SAI2_B STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN3)
|
||||
#define DMAMAP_QUADSPI STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN3)
|
||||
|
||||
#define DMAMAP_SPI4_RX_1 STM32_DMA_MAP(DMA2,DMA_STREAM0,DMA_CHAN4)
|
||||
#define DMAMAP_SPI4_TX_1 STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN4)
|
||||
#define DMAMAP_USART1_RX_1 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN4)
|
||||
#define DMAMAP_SDMMC1_1 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN4)
|
||||
#define DMAMAP_USART1_RX_2 STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN4)
|
||||
#define DMAMAP_SDMMC1_2 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN4)
|
||||
#define DMAMAP_USART1_TX STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN4)
|
||||
|
||||
#define DMAMAP_USART6_RX_1 STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN5)
|
||||
#define DMAMAP_USART6_RX_2 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN5)
|
||||
#define DMAMAP_SPI4_RX_2 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN5)
|
||||
#define DMAMAP_SPI4_TX_2 STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN5)
|
||||
#define DMAMAP_USART6_TX_1 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN5)
|
||||
#define DMAMAP_USART6_TX_2 STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN5)
|
||||
|
||||
#define DMAMAP_TIM1_TRIG_1 STM32_DMA_MAP(DMA2,DMA_STREAM0,DMA_CHAN6)
|
||||
#define DMAMAP_TIM1_CH1_2 STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN6)
|
||||
#define DMAMAP_TIM1_CH2_2 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN6)
|
||||
#define DMAMAP_TIM1_CH1 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN6)
|
||||
#define DMAMAP_TIM1_CH4 STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN6)
|
||||
#define DMAMAP_TIM1_TRIG_2 STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN6)
|
||||
#define DMAMAP_TIM1_COM STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN6)
|
||||
#define DMAMAP_TIM1_UP STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN6)
|
||||
#define DMAMAP_TIM1_CH3_2 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN6)
|
||||
|
||||
#define DMAMAP_TIM8_UP STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN7)
|
||||
#define DMAMAP_TIM8_CH1_2 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN7)
|
||||
#define DMAMAP_TIM8_CH2_2 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN7)
|
||||
#define DMAMAP_TIM8_CH3_2 STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN7)
|
||||
#define DMAMAP_SPI5_RX_2 STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN7)
|
||||
#define DMAMAP_SPI5_TX_2 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN7)
|
||||
#define DMAMAP_TIM8_CH4 STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN7)
|
||||
#define DMAMAP_TIM8_TRIG STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN7)
|
||||
#define DMAMAP_TIM8_COM STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN7)
|
||||
|
||||
#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */
|
||||
#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XXX75XX_DMA_H */
|
||||
@ -41,7 +41,8 @@
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "chip.h"
|
||||
|
||||
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
@ -153,4 +154,5 @@
|
||||
#define PWR_CSR2_EWUP5 (1 << 12) /* Bit 12: Enable wakeup pin for PI8 */
|
||||
#define PWR_CSR2_EWUP6 (1 << 13) /* Bit 13: Enable wakeup pin for PI11 */
|
||||
|
||||
#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */
|
||||
#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_PWR_H */
|
||||
|
||||
294
arch/arm/src/stm32f7/stm32_dma.h
Normal file
294
arch/arm/src/stm32f7/stm32_dma.h
Normal file
@ -0,0 +1,294 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32f7/stm32_dma.h
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32F7_STM32_DMA_H
|
||||
#define __ARCH_ARM_SRC_STM32F7_STM32_DMA_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <sys/types.h>
|
||||
|
||||
#include "chip/stm32_dma.h"
|
||||
|
||||
/* These definitions provide the bit encoding of the 'status' parameter passed to the
|
||||
* DMA callback function (see dma_callback_t).
|
||||
*/
|
||||
|
||||
#define DMA_STATUS_FEIF 0 /* Stream FIFO error (ignored) */
|
||||
#define DMA_STATUS_DMEIF DMA_STREAM_DMEIF_BIT /* Stream direct mode error */
|
||||
#define DMA_STATUS_TEIF DMA_STREAM_TEIF_BIT /* Stream Transfer Error */
|
||||
#define DMA_STATUS_HTIF DMA_STREAM_HTIF_BIT /* Stream Half Transfer */
|
||||
#define DMA_STATUS_TCIF DMA_STREAM_TCIF_BIT /* Stream Transfer Complete */
|
||||
|
||||
#define DMA_STATUS_ERROR (DMA_STATUS_FEIF|DMA_STATUS_DMEIF|DMA_STATUS_TEIF)
|
||||
#define DMA_STATUS_SUCCESS (DMA_STATUS_TCIF|DMA_STATUS_HTIF)
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/* DMA_HANDLE provides an opaque are reference that can be used to represent a DMA
|
||||
* channel (F1) or a DMA stream (F4).
|
||||
*/
|
||||
|
||||
typedef FAR void *DMA_HANDLE;
|
||||
|
||||
/* Description:
|
||||
* This is the type of the callback that is used to inform the user of the the
|
||||
* completion of the DMA.
|
||||
*
|
||||
* Input Parameters:
|
||||
* handle - Refers tot he DMA channel or stream
|
||||
* status - A bit encoded value that provides the completion status. See the
|
||||
* DMASTATUS_* definitions above.
|
||||
* arg - A user-provided value that was provided when stm32_dmastart() was
|
||||
* called.
|
||||
*/
|
||||
|
||||
typedef void (*dma_callback_t)(DMA_HANDLE handle, uint8_t status, void *arg);
|
||||
|
||||
struct stm32_dmaregs_s
|
||||
{
|
||||
uint32_t lisr;
|
||||
uint32_t hisr;
|
||||
uint32_t scr;
|
||||
uint32_t sndtr;
|
||||
uint32_t spar;
|
||||
uint32_t sm0ar;
|
||||
uint32_t sm1ar;
|
||||
uint32_t sfcr;
|
||||
};
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_dmachannel
|
||||
*
|
||||
* Description:
|
||||
* Allocate a DMA channel. This function gives the caller mutually
|
||||
* exclusive access to the DMA channel specified by the 'chan' argument.
|
||||
* DMA channels are shared on the STM32: Devices sharing the same DMA
|
||||
* channel cannot do DMA concurrently! See the DMACHAN_* definitions in
|
||||
* stm32_dma.h.
|
||||
*
|
||||
* If the DMA channel is not available, then stm32_dmachannel() will wait
|
||||
* until the holder of the channel relinquishes the channel by calling
|
||||
* stm32_dmafree(). WARNING: If you have two devices sharing a DMA
|
||||
* channel and the code never releases the channel, the stm32_dmachannel
|
||||
* call for the other will hang forever in this function! Don't let your
|
||||
* design do that!
|
||||
*
|
||||
* Hmm.. I suppose this interface could be extended to make a non-blocking
|
||||
* version. Feel free to do that if that is what you need.
|
||||
*
|
||||
* Input parameter:
|
||||
* chan - Identifies the stream/channel resource
|
||||
* For the STM32 F1, this is simply the channel number as provided by
|
||||
* the DMACHAN_* definitions in chip/stm32f10xxx_dma.h.
|
||||
* For the STM32 F4, this is a bit encoded value as provided by the
|
||||
* the DMAMAP_* definitions in chip/stm32f40xxx_dma.h
|
||||
*
|
||||
* Returned Value:
|
||||
* Provided that 'chan' is valid, this function ALWAYS returns a non-NULL,
|
||||
* void* DMA channel handle. (If 'chan' is invalid, the function will
|
||||
* assert if debug is enabled or do something ignorant otherwise).
|
||||
*
|
||||
* Assumptions:
|
||||
* - The caller does not hold he DMA channel.
|
||||
* - The caller can wait for the DMA channel to be freed if it is no
|
||||
* available.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
DMA_HANDLE stm32_dmachannel(unsigned int chan);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_dmafree
|
||||
*
|
||||
* Description:
|
||||
* Release a DMA channel. If another thread is waiting for this DMA channel
|
||||
* in a call to stm32_dmachannel, then this function will re-assign the
|
||||
* DMA channel to that thread and wake it up. NOTE: The 'handle' used
|
||||
* in this argument must NEVER be used again until stm32_dmachannel() is
|
||||
* called again to re-gain access to the channel.
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
* Assumptions:
|
||||
* - The caller holds the DMA channel.
|
||||
* - There is no DMA in progress
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_dmafree(DMA_HANDLE handle);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_dmasetup
|
||||
*
|
||||
* Description:
|
||||
* Configure DMA before using
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr,
|
||||
size_t ntransfers, uint32_t ccr);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_dmastart
|
||||
*
|
||||
* Description:
|
||||
* Start the DMA transfer
|
||||
*
|
||||
* Assumptions:
|
||||
* - DMA handle allocated by stm32_dmachannel()
|
||||
* - No DMA in progress
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg,
|
||||
bool half);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_dmastop
|
||||
*
|
||||
* Description:
|
||||
* Cancel the DMA. After stm32_dmastop() is called, the DMA channel is
|
||||
* reset and stm32_dmasetup() must be called before stm32_dmastart() can be
|
||||
* called again
|
||||
*
|
||||
* Assumptions:
|
||||
* - DMA handle allocated by stm32_dmachannel()
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_dmastop(DMA_HANDLE handle);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_dmaresidual
|
||||
*
|
||||
* Description:
|
||||
* Returns the number of bytes remaining to be transferred
|
||||
*
|
||||
* Assumptions:
|
||||
* - DMA handle allocated by stm32_dmachannel()
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
size_t stm32_dmaresidual(DMA_HANDLE handle);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_dmacapable
|
||||
*
|
||||
* Description:
|
||||
* Check if the DMA controller can transfer data to/from given memory
|
||||
* address with the given configuration. This depends on the internal
|
||||
* connections in the ARM bus matrix of the processor. Note that this
|
||||
* only applies to memory addresses, it will return false for any peripheral
|
||||
* address.
|
||||
*
|
||||
* Returned value:
|
||||
* True, if transfer is possible.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_STM32_DMACAPABLE
|
||||
bool stm32_dmacapable(uintptr_t maddr, uint32_t count, uint32_t ccr);
|
||||
#else
|
||||
# define stm32_dmacapable(maddr, count, ccr) (true)
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_dmasample
|
||||
*
|
||||
* Description:
|
||||
* Sample DMA register contents
|
||||
*
|
||||
* Assumptions:
|
||||
* - DMA handle allocated by stm32_dmachannel()
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_DEBUG_DMA
|
||||
void stm32_dmasample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs);
|
||||
#else
|
||||
# define stm32_dmasample(handle,regs)
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_dmadump
|
||||
*
|
||||
* Description:
|
||||
* Dump previously sampled DMA register contents
|
||||
*
|
||||
* Assumptions:
|
||||
* - DMA handle allocated by stm32_dmachannel()
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_DEBUG_DMA
|
||||
void stm32_dmadump(DMA_HANDLE handle, const struct stm32_dmaregs_s *regs,
|
||||
const char *msg);
|
||||
#else
|
||||
# define stm32_dmadump(handle,regs,msg)
|
||||
#endif
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_STM32F7_STM32_DMA_H */
|
||||
Loading…
Reference in New Issue
Block a user