From 03e9f936d90c77037f28a30b58b717c7f389d71f Mon Sep 17 00:00:00 2001 From: Nathan Hartman <59230071+hartmannathan@users.noreply.github.com> Date: Fri, 30 Oct 2020 09:57:03 -0400 Subject: [PATCH] tiva/cc13x2_cc26x2: Fix syntax error arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_adi3_refsys.h: * Fix syntax error. The define ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_MIN had an unintentional comment closing "*/" in the middle of its name. --- .../src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_adi3_refsys.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_adi3_refsys.h b/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_adi3_refsys.h index 5a473fe0de..aaa563f7c0 100644 --- a/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_adi3_refsys.h +++ b/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_adi3_refsys.h @@ -205,7 +205,7 @@ # define ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_DEFAULT (0 << ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_SHIFT) /* Default, about 1.63V */ # define ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_TYPICAL (5 << ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_SHIFT) /* Typical voltage after trim voltage 1.71V */ # define ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_MAX (21 << ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_SHIFT) /* Max voltage 1.96V */ -# define ADI3_REFS */YS_DCDCCTL0_VDDR_TRIM_MIN (22 << ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_SHIFT) /* Min voltage 1.47V */ +# define ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_MIN (22 << ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_SHIFT) /* Min voltage 1.47V */ #define ADI3_REFSYS_DCDCCTL0_GLDO_ISRC_SHIFT (5) /* Bits 5-7: Set charge and re-charge current level */ /* 2's complement encoding */ #define ADI3_REFSYS_DCDCCTL0_GLDO_ISRC_MASK (7 << ADI3_REFSYS_DCDCCTL0_GLDO_ISRC_SHIFT)