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TMS570: Add selftest configuration option; Add a few more SYS register definitions

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This commit is contained in:
Gregory Nutt 2015-12-18 09:09:58 -06:00
parent d4b7bf59d0
commit 0403132800
3 changed files with 23 additions and 9 deletions
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6
arch/arm/src/tms570/Kconfig
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@ -84,4 +84,10 @@ config TMS570_SCI1
endmenu # TMS570 Peripheral Support endmenu # TMS570 Peripheral Support
config TMS570_SELFTEST
bool "Power-on Selftest"
default n
---help---
Enable power-on self-test of memories and ECC logic.
endif # ARCH_CHIP_TMS570 endif # ARCH_CHIP_TMS570

12
arch/arm/src/tms570/chip/tms570_sys.h
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@ -290,7 +290,17 @@
/* System Exception Control Register */ /* System Exception Control Register */
#define SYS_ECR_ #define SYS_ECR_
/* System Exception Status Register */ /* System Exception Status Register */
#define SYS_ESR_
#define SYS_ESR_MPMODE (1 << 0) /* Bit 0: Current memory protection unit (MPU) mode */
#define SYS_ESR_EXTRST (1 << 3) /* Bit 3: External reset flag */
#define SYS_ESR_SWRST (1 << 4) /* Bit 4: Software reset flag */
#define SYS_ESR_CPURST (1 << 5) /* Bit 5: CPU reset flag */
#define SYS_ESR_WDRST (1 << 13) /* Bit 13: Watchdog reset flag */
#define SYS_ESR_OSCRST (1 << 14) /* Bit 14: Reset caused by an oscillator failure or PLL cycle slip */
#define SYS_ESR_PORST (1 << 15) /* Bit 15: Power-up reset */
#define SYS_ESR_RSTALL (0x0000e038)
/* System Test Abort Status Register */ /* System Test Abort Status Register */
#define SYS_TASR_ #define SYS_TASR_
/* Global Status Register */ /* Global Status Register */

14
arch/arm/src/tms570/tms570_boot.c
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@ -196,7 +196,6 @@ void arm_boot(void)
tms570_event_export(); tms570_event_export();
#if 0 // REVISIT: Need SYS header file
/* Read from the system exception status register to identify the cause of /* Read from the system exception status register to identify the cause of
* the CPU reset. * the CPU reset.
* *
@ -205,12 +204,11 @@ void arm_boot(void)
* to do that. * to do that.
*/ */
DEBUGASSERT((getreg(TMS570_SYS_SYSESR) & SYS_ESR_PORST) != 0); DEBUGASSERT((getreg(TMS570_SYS_ESR) & SYS_ESR_PORST) != 0);
/* Clear all reset status flags on successful power on reset */ /* Clear all reset status flags on successful power on reset */
putreg32(SYS_ESR_ALLRST, TMS570_SYS_SYSESR); putreg32(SYS_ESR_RSTALL, TMS570_SYS_ESR);
#endif
/* Check if there were ESM group3 errors during power-up. /* Check if there were ESM group3 errors during power-up.
* *
@ -230,7 +228,7 @@ void arm_boot(void)
tms570_clockconfig(); tms570_clockconfig();
#ifdef CONFIG_TMS570_BIST #ifdef CONFIG_TMS570_SELFTEST
/* Run a diagnostic check on the memory self-test controller. */ /* Run a diagnostic check on the memory self-test controller. */
# warning Missing logic # warning Missing logic
@ -239,7 +237,7 @@ void arm_boot(void)
/* Disable PBIST clocks and disable memory self-test mode */ /* Disable PBIST clocks and disable memory self-test mode */
# warning Missing logic # warning Missing logic
#endif /* CONFIG_TMS570_BIST */ #endif /* CONFIG_TMS570_SELFTEST */
/* Initialize CPU RAM. */ /* Initialize CPU RAM. */
@ -249,14 +247,14 @@ void arm_boot(void)
tms570_enable_ramecc(); tms570_enable_ramecc();
#ifdef CONFIG_TMS570_BIST #ifdef CONFIG_TMS570_SELFTEST
/* Perform PBIST on all dual-port memories */ /* Perform PBIST on all dual-port memories */
#warning Missing logic #warning Missing logic
/* Test the CPU ECC mechanism for RAM accesses. */ /* Test the CPU ECC mechanism for RAM accesses. */
#warning Missing logic #warning Missing logic
#endif /* CONFIG_TMS570_BIST */ #endif /* CONFIG_TMS570_SELFTEST */
/* Release the MibSPI1 modules from local reset. */ /* Release the MibSPI1 modules from local reset. */
#warning Missing logic #warning Missing logic