arch/arm/include/nrf52/ and arch/arm/src/nrf52: 1. Added 52840 family support 2. Use common irq and memory layout header file for 52832 & 52840.
This commit is contained in:
Levin Li
Gregory Nutt
parent
f6b00e1966
commit
043df95d8d
@ -1,5 +1,5 @@
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/********************************************************************************************
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* arch/arm/include/nrf52xxx/irq.h
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* arch/arm/include/nrf52/irq.h
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*
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* Copyright (C) 2018 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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@ -77,8 +77,8 @@
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/* Cortex-M4 External interrupts (vectors >= 16) */
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#if defined(CONFIG_ARCH_FAMILY_NRF52832)
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# include <arch/nrf52/nrf52832_irq.h>
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#if defined(CONFIG_ARCH_FAMILY_NRF52832) || defined(CONFIG_ARCH_FAMILY_NRF52840)
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# include <arch/nrf52/nrf52_irq.h>
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#else
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# error "Unsupported NRF52XX MCU"
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#endif
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@ -46,18 +46,18 @@
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/* Cortex-M4 External interrupts (vectors >= 16) */
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#define NRF52_IRQ_POWER_CLOCK (NRF52_IRQ_EXTINT+0) /* VOD Windowed watchdog timer, Brownout detect */
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#define NRF52_IRQ_RADIO (NRF52_IRQ_EXTINT+1) /* DMA controller */
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#define NRF52_IRQ_UART0 (NRF52_IRQ_EXTINT+2) /* GPIO group 0 */
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#define NRF52_IRQ_SPI_TWI_0 (NRF52_IRQ_EXTINT+3) /* GPIO group 1 */
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#define NRF52_IRQ_SPI_TWI_1 (NRF52_IRQ_EXTINT+4) /* Pin interrupt 0 or pattern match engine slice 0 */
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#define NRF52_IRQ_NFCT (NRF52_IRQ_EXTINT+5) /* Pin interrupt 1 or pattern match engine slice 1 */
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#define NRF52_IRQ_GPIOTE (NRF52_IRQ_EXTINT+6) /* Pin interrupt 2 or pattern match engine slice 2 */
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#define NRF52_IRQ_SAADC (NRF52_IRQ_EXTINT+7) /* Pin interrupt 3 or pattern match engine slice 3 */
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#define NRF52_IRQ_TIMER0 (NRF52_IRQ_EXTINT+8) /* Micro-tick Timer */
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#define NRF52_IRQ_TIMER1 (NRF52_IRQ_EXTINT+9) /* Multi-rate timer */
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#define NRF52_IRQ_TIMER2 (NRF52_IRQ_EXTINT+10) /* Standard counter/timer CTIMER0 */
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#define NRF52_IRQ_RTC0 (NRF52_IRQ_EXTINT+11) /* Standard counter/timer CTIMER1 */
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#define NRF52_IRQ_POWER_CLOCK (NRF52_IRQ_EXTINT+0) /* Power, Clock, Bprot */
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#define NRF52_IRQ_RADIO (NRF52_IRQ_EXTINT+1) /* Radio controller */
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#define NRF52_IRQ_UART0 (NRF52_IRQ_EXTINT+2) /* UART/UARTE 0 */
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#define NRF52_IRQ_SPI_TWI_0 (NRF52_IRQ_EXTINT+3) /* SPI / TWI 0 */
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#define NRF52_IRQ_SPI_TWI_1 (NRF52_IRQ_EXTINT+4) /* SPI / TWI 1 */
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#define NRF52_IRQ_NFCT (NRF52_IRQ_EXTINT+5) /* NFCT */
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#define NRF52_IRQ_GPIOTE (NRF52_IRQ_EXTINT+6) /* GPIO Task & Event */
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#define NRF52_IRQ_SAADC (NRF52_IRQ_EXTINT+7) /* Analog to Digital Converter */
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#define NRF52_IRQ_TIMER0 (NRF52_IRQ_EXTINT+8) /* Timer 0 */
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#define NRF52_IRQ_TIMER1 (NRF52_IRQ_EXTINT+9) /* Timer 1 */
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#define NRF52_IRQ_TIMER2 (NRF52_IRQ_EXTINT+10) /* Timer 2 */
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#define NRF52_IRQ_RTC0 (NRF52_IRQ_EXTINT+11) /* Real-time counter 0 */
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#define NRF52_IRQ_TEMP (NRF52_IRQ_EXTINT+12) /* Temperature Sensor */
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#define NRF52_IRQ_RNG (NRF52_IRQ_EXTINT+13) /* Random Number Generator */
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#define NRF52_IRQ_ECB (NRF52_IRQ_EXTINT+14) /* AES ECB Mode Encryption */
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@ -86,7 +86,18 @@
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#define NRF52_IRQ_I2S (NRF52_IRQ_EXTINT+37) /* Inter-IC Sound interface */
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#define NRF52_IRQ_FPU (NRF52_IRQ_EXTINT+38) /* FPU interrupt */
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#if defined(CONFIG_ARCH_FAMILY_NRF52840)
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#define NRF52_IRQ_USBD (NRF52_IRQ_EXTINT+39) /* USB device */
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#define NRF52_IRQ_UARTE1 (NRF52_IRQ_EXTINT+40) /* UARTE 1 */
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#define NRF52_IRQ_QSPI (NRF52_IRQ_EXTINT+41) /* Quad SPI */
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#define NRF52_IRQ_PWM3 (NRF52_IRQ_EXTINT+45) /* Pulse Width Modulation Unit 3 */
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#define NRF52_IRQ_SPIM3 (NRF52_IRQ_EXTINT+47) /* SPI Master 3 */
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#define NRF52_IRQ_NEXTINT (48)
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#else
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#define NRF52_IRQ_NEXTINT (39)
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#endif
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#define NRF52_IRQ_NIRQS (NRF52_IRQ_EXTINT+NRF52_IRQ_NEXTINT)
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/* Total number of IRQ numbers */
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@ -17,6 +17,13 @@ config ARCH_CHIP_NRF52832
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#select NRF52_HAVE_I2C_MASTER
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#select NRF52_HAVE_UART
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config ARCH_CHIP_NRF52840
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bool "NRF52840"
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select ARCH_FAMILY_NRF52
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select ARCH_FAMILY_NRF52840
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#select NRF52_HAVE_I2C_MASTER
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#select NRF52_HAVE_UART
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endchoice # NRF52 Chip Selection
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# NRF52 Families
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@ -29,6 +36,10 @@ config ARCH_FAMILY_NRF52832
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bool
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default n
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config ARCH_FAMILY_NRF52840
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bool
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default n
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# Peripheral support
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# Peripheral Selection
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@ -63,6 +74,15 @@ config NRF52_UART0
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select UART0_SERIALDRIVER
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select NRF52_HAVE_UART
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config NRF52_RNG
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bool "Random Generator"
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default n
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config NRF52_QSPI
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bool "QSPI"
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default n
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depends on ARCH_CHIP_NRF52840
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config NRF52_WDT
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bool "Watchdog (WDT)"
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default n
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@ -1,126 +0,0 @@
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/****************************************************************************
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* arch/arm/src/nrf52/chip/nrf52832_memorymap.h
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*
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* Copyright (C) 2018 Gregory Nutt. All rights reserved.
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* Author: Janne Rosberg <janne@offcode.fi>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_NRF52_CHIP_NRF52832_MEMORYMAP_H
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#define __ARCH_ARM_SRC_NRF52_CHIP_NRF52832_MEMORYMAP_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Memory Map */
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#define NRF52_FLASH_BASE 0x00000000 /* Flash memory (512 KB) */
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#define NRF52_SRAM_BASE 0x20000000 /* SRAM bank (64 KB) */
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#define NRF52_FICR_BASE 0x10000000 /* FICR */
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#define NRF52_UICR_BASE 0x10001000 /* UICR */
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#define NRF52_APB0_BASE 0x40000000 /* APB */
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#define NRF52_CORTEXM4_BASE 0xe0000000 /* Cortex-M4 Private Peripheral Bus */
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/* APB Peripherals */
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#define NRF52_CLOCK_BASE 0x40000000
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#define NRF52_POWER_BASE 0x40000000
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#define NRF52_BPROT_BASE 0x40000000
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#define NRF52_RADIO_BASE 0x40001000
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#define NRF52_UARTE0_BASE 0x40002000
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#define NRF52_UART0_BASE 0x40002000
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#define NRF52_SPIM0_BASE 0x40003000
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#define NRF52_SPIS0_BASE 0x40003000
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#define NRF52_TWIM0_BASE 0x40003000
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#define NRF52_TWI0_BASE 0x40003000
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#define NRF52_SPI0_BASE 0x40003000
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#define NRF52_TWIS0_BASE 0x40003000
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#define NRF52_SPIM1_BASE 0x40004000
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#define NRF52_TWI1_BASE 0x40004000
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#define NRF52_SPIS1_BASE 0x40004000
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#define NRF52_TWIS1_BASE 0x40004000
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#define NRF52_TWIM1_BASE 0x40004000
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#define NRF52_SPI1_BASE 0x40004000
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#define NRF52_NFCT_BASE 0x40005000
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#define NRF52_GPIOTE_BASE 0x40006000
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#define NRF52_SAADC_BASE 0x40007000
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#define NRF52_TIMER0_BASE 0x40008000
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#define NRF52_TIMER1_BASE 0x40009000
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#define NRF52_TIMER2_BASE 0x4000A000
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#define NRF52_RTC0_BASE 0x4000B000
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#define NRF52_TEMP_BASE 0x4000C000
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#define NRF52_RNG_BASE 0x4000D000
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#define NRF52_ECB_BASE 0x4000E000
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#define NRF52_CCM_BASE 0x4000F000
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#define NRF52_AAR_BASE 0x4000F000
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#define NRF52_WDT_BASE 0x40010000
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#define NRF52_RTC1_BASE 0x40011000
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#define NRF52_QDEC_BASE 0x40012000
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#define NRF52_LPCOMP_BASE 0x40013000
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#define NRF52_COMP_BASE 0x40013000
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#define NRF52_SWI0_BASE 0x40014000
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#define NRF52_EGU0_BASE 0x40014000
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#define NRF52_EGU1_BASE 0x40015000
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#define NRF52_SWI1_BASE 0x40015000
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#define NRF52_SWI2_BASE 0x40016000
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#define NRF52_EGU2_BASE 0x40016000
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#define NRF52_SWI3_BASE 0x40017000
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#define NRF52_EGU3_BASE 0x40017000
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#define NRF52_EGU4_BASE 0x40018000
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#define NRF52_SWI4_BASE 0x40018000
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#define NRF52_SWI5_BASE 0x40019000
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#define NRF52_EGU5_BASE 0x40019000
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#define NRF52_TIMER3_BASE 0x4001A000
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#define NRF52_TIMER4_BASE 0x4001B000
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#define NRF52_PWM0_BASE 0x4001C000
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#define NRF52_PDM_BASE 0x4001D000
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#define NRF52_NVMC_BASE 0x4001E000
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#define NRF52_PPI_BASE 0x4001F000
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#define NRF52_MWU_BASE 0x40020000
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#define NRF52_PWM1_BASE 0x40021000
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#define NRF52_PWM2_BASE 0x40022000
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#define NRF52_SPI2_BASE 0x40023000
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#define NRF52_SPIS2_BASE 0x40023000
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#define NRF52_SPIM2_BASE 0x40023000
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#define NRF52_RTC2_BASE 0x40024000
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#define NRF52_I2S_BASE 0x40025000
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#define NRF52_FPU_BASE 0x40026000
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#define NRF52_GPIO_P0_BASE 0x50000000
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#endif /* __ARCH_ARM_SRC_NRF52_CHIP_NRF52832_MEMORYMAP_H */
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@ -1,4 +1,4 @@
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/************************************************************************************
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/****************************************************************************
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* arch/arm/src/nrf52/chip/nrf52_memorymap.h
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*
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* Copyright (C) 2018 Gregory Nutt. All rights reserved.
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@ -31,22 +31,103 @@
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_NRF52_CHIP_NRF52_MEMORYMAP_H
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#define __ARCH_ARM_SRC_NRF52_CHIP_NRF52_MEMORYMAP_H
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/************************************************************************************
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/****************************************************************************
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* Included Files
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************************************************************************************/
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****************************************************************************/
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#include <nuttx/config.h>
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#if defined(CONFIG_ARCH_FAMILY_NRF52832)
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# include "chip/nrf52832_memorymap.h"
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#else
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# error "Unsupported NRF52 family"
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#endif
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Memory Map */
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#define NRF52_FLASH_BASE 0x00000000 /* Flash memory Start Address */
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#define NRF52_SRAM_BASE 0x20000000 /* SRAM Start Address */
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#define NRF52_FICR_BASE 0x10000000 /* FICR */
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#define NRF52_UICR_BASE 0x10001000 /* UICR */
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#define NRF52_APB0_BASE 0x40000000 /* APB */
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#define NRF52_CORTEXM4_BASE 0xe0000000 /* Cortex-M4 Private Peripheral Bus */
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/* APB Peripherals */
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#define NRF52_CLOCK_BASE 0x40000000
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#define NRF52_POWER_BASE 0x40000000
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#define NRF52_BPROT_BASE 0x40000000
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#define NRF52_RADIO_BASE 0x40001000
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#define NRF52_UARTE0_BASE 0x40002000
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#define NRF52_UART0_BASE 0x40002000
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#define NRF52_SPIM0_BASE 0x40003000
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#define NRF52_SPIS0_BASE 0x40003000
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#define NRF52_TWIM0_BASE 0x40003000
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#define NRF52_TWI0_BASE 0x40003000
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#define NRF52_SPI0_BASE 0x40003000
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#define NRF52_TWIS0_BASE 0x40003000
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#define NRF52_SPIM1_BASE 0x40004000
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#define NRF52_TWI1_BASE 0x40004000
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#define NRF52_SPIS1_BASE 0x40004000
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#define NRF52_TWIS1_BASE 0x40004000
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#define NRF52_TWIM1_BASE 0x40004000
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#define NRF52_SPI1_BASE 0x40004000
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#define NRF52_NFCT_BASE 0x40005000
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#define NRF52_GPIOTE_BASE 0x40006000
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#define NRF52_SAADC_BASE 0x40007000
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#define NRF52_TIMER0_BASE 0x40008000
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#define NRF52_TIMER1_BASE 0x40009000
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#define NRF52_TIMER2_BASE 0x4000a000
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#define NRF52_RTC0_BASE 0x4000b000
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#define NRF52_TEMP_BASE 0x4000c000
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#define NRF52_RNG_BASE 0x4000d000
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#define NRF52_ECB_BASE 0x4000e000
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#define NRF52_CCM_BASE 0x4000f000
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#define NRF52_AAR_BASE 0x4000f000
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#define NRF52_WDT_BASE 0x40010000
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#define NRF52_RTC1_BASE 0x40011000
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#define NRF52_QDEC_BASE 0x40012000
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#define NRF52_LPCOMP_BASE 0x40013000
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#define NRF52_COMP_BASE 0x40013000
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#define NRF52_SWI0_BASE 0x40014000
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#define NRF52_EGU0_BASE 0x40014000
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#define NRF52_EGU1_BASE 0x40015000
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#define NRF52_SWI1_BASE 0x40015000
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#define NRF52_SWI2_BASE 0x40016000
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#define NRF52_EGU2_BASE 0x40016000
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#define NRF52_SWI3_BASE 0x40017000
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#define NRF52_EGU3_BASE 0x40017000
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#define NRF52_EGU4_BASE 0x40018000
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#define NRF52_SWI4_BASE 0x40018000
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#define NRF52_SWI5_BASE 0x40019000
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#define NRF52_EGU5_BASE 0x40019000
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#define NRF52_TIMER3_BASE 0x4001a000
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#define NRF52_TIMER4_BASE 0x4001b000
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#define NRF52_PWM0_BASE 0x4001c000
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#define NRF52_PDM_BASE 0x4001d000
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#define NRF52_NVMC_BASE 0x4001e000
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#define NRF52_PPI_BASE 0x4001f000
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#define NRF52_MWU_BASE 0x40020000
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#define NRF52_PWM1_BASE 0x40021000
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#define NRF52_PWM2_BASE 0x40022000
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#define NRF52_SPI2_BASE 0x40023000
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#define NRF52_SPIS2_BASE 0x40023000
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#define NRF52_SPIM2_BASE 0x40023000
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#define NRF52_RTC2_BASE 0x40024000
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#define NRF52_I2S_BASE 0x40025000
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#define NRF52_FPU_BASE 0x40026000
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#define NRF52_USBD_BASE 0x40027000
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#define NRF52_UARTE1_BASE 0x40028000
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#define NRF52_QSPI_BASE 0x40029000
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#define NRF52_PWM3_BASE 0x4002d000
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#define NRF52_SPIM3_BASE 0x4002f000
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#define NRF52_GPIO_P0_BASE 0x50000000
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#define NRF52_GPIO_P1_BASE 0x50003000
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#endif /* __ARCH_ARM_SRC_NRF52_CHIP_NRF52_MEMORYMAP_H */
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