diff --git a/arch/arm/include/nrf52/irq.h b/arch/arm/include/nrf52/irq.h index 439721d0c9..e337edb28d 100644 --- a/arch/arm/include/nrf52/irq.h +++ b/arch/arm/include/nrf52/irq.h @@ -1,5 +1,5 @@ /******************************************************************************************** - * arch/arm/include/nrf52xxx/irq.h + * arch/arm/include/nrf52/irq.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -77,8 +77,8 @@ /* Cortex-M4 External interrupts (vectors >= 16) */ -#if defined(CONFIG_ARCH_FAMILY_NRF52832) -# include +#if defined(CONFIG_ARCH_FAMILY_NRF52832) || defined(CONFIG_ARCH_FAMILY_NRF52840) +# include #else # error "Unsupported NRF52XX MCU" #endif diff --git a/arch/arm/include/nrf52/nrf52832_irq.h b/arch/arm/include/nrf52/nrf52_irq.h similarity index 78% rename from arch/arm/include/nrf52/nrf52832_irq.h rename to arch/arm/include/nrf52/nrf52_irq.h index 0f043c58ba..641aa9bb51 100644 --- a/arch/arm/include/nrf52/nrf52832_irq.h +++ b/arch/arm/include/nrf52/nrf52_irq.h @@ -46,18 +46,18 @@ /* Cortex-M4 External interrupts (vectors >= 16) */ -#define NRF52_IRQ_POWER_CLOCK (NRF52_IRQ_EXTINT+0) /* VOD Windowed watchdog timer, Brownout detect */ -#define NRF52_IRQ_RADIO (NRF52_IRQ_EXTINT+1) /* DMA controller */ -#define NRF52_IRQ_UART0 (NRF52_IRQ_EXTINT+2) /* GPIO group 0 */ -#define NRF52_IRQ_SPI_TWI_0 (NRF52_IRQ_EXTINT+3) /* GPIO group 1 */ -#define NRF52_IRQ_SPI_TWI_1 (NRF52_IRQ_EXTINT+4) /* Pin interrupt 0 or pattern match engine slice 0 */ -#define NRF52_IRQ_NFCT (NRF52_IRQ_EXTINT+5) /* Pin interrupt 1 or pattern match engine slice 1 */ -#define NRF52_IRQ_GPIOTE (NRF52_IRQ_EXTINT+6) /* Pin interrupt 2 or pattern match engine slice 2 */ -#define NRF52_IRQ_SAADC (NRF52_IRQ_EXTINT+7) /* Pin interrupt 3 or pattern match engine slice 3 */ -#define NRF52_IRQ_TIMER0 (NRF52_IRQ_EXTINT+8) /* Micro-tick Timer */ -#define NRF52_IRQ_TIMER1 (NRF52_IRQ_EXTINT+9) /* Multi-rate timer */ -#define NRF52_IRQ_TIMER2 (NRF52_IRQ_EXTINT+10) /* Standard counter/timer CTIMER0 */ -#define NRF52_IRQ_RTC0 (NRF52_IRQ_EXTINT+11) /* Standard counter/timer CTIMER1 */ +#define NRF52_IRQ_POWER_CLOCK (NRF52_IRQ_EXTINT+0) /* Power, Clock, Bprot */ +#define NRF52_IRQ_RADIO (NRF52_IRQ_EXTINT+1) /* Radio controller */ +#define NRF52_IRQ_UART0 (NRF52_IRQ_EXTINT+2) /* UART/UARTE 0 */ +#define NRF52_IRQ_SPI_TWI_0 (NRF52_IRQ_EXTINT+3) /* SPI / TWI 0 */ +#define NRF52_IRQ_SPI_TWI_1 (NRF52_IRQ_EXTINT+4) /* SPI / TWI 1 */ +#define NRF52_IRQ_NFCT (NRF52_IRQ_EXTINT+5) /* NFCT */ +#define NRF52_IRQ_GPIOTE (NRF52_IRQ_EXTINT+6) /* GPIO Task & Event */ +#define NRF52_IRQ_SAADC (NRF52_IRQ_EXTINT+7) /* Analog to Digital Converter */ +#define NRF52_IRQ_TIMER0 (NRF52_IRQ_EXTINT+8) /* Timer 0 */ +#define NRF52_IRQ_TIMER1 (NRF52_IRQ_EXTINT+9) /* Timer 1 */ +#define NRF52_IRQ_TIMER2 (NRF52_IRQ_EXTINT+10) /* Timer 2 */ +#define NRF52_IRQ_RTC0 (NRF52_IRQ_EXTINT+11) /* Real-time counter 0 */ #define NRF52_IRQ_TEMP (NRF52_IRQ_EXTINT+12) /* Temperature Sensor */ #define NRF52_IRQ_RNG (NRF52_IRQ_EXTINT+13) /* Random Number Generator */ #define NRF52_IRQ_ECB (NRF52_IRQ_EXTINT+14) /* AES ECB Mode Encryption */ @@ -86,7 +86,18 @@ #define NRF52_IRQ_I2S (NRF52_IRQ_EXTINT+37) /* Inter-IC Sound interface */ #define NRF52_IRQ_FPU (NRF52_IRQ_EXTINT+38) /* FPU interrupt */ +#if defined(CONFIG_ARCH_FAMILY_NRF52840) +#define NRF52_IRQ_USBD (NRF52_IRQ_EXTINT+39) /* USB device */ +#define NRF52_IRQ_UARTE1 (NRF52_IRQ_EXTINT+40) /* UARTE 1 */ +#define NRF52_IRQ_QSPI (NRF52_IRQ_EXTINT+41) /* Quad SPI */ +#define NRF52_IRQ_PWM3 (NRF52_IRQ_EXTINT+45) /* Pulse Width Modulation Unit 3 */ +#define NRF52_IRQ_SPIM3 (NRF52_IRQ_EXTINT+47) /* SPI Master 3 */ + +#define NRF52_IRQ_NEXTINT (48) +#else #define NRF52_IRQ_NEXTINT (39) +#endif + #define NRF52_IRQ_NIRQS (NRF52_IRQ_EXTINT+NRF52_IRQ_NEXTINT) /* Total number of IRQ numbers */ diff --git a/arch/arm/src/nrf52/Kconfig b/arch/arm/src/nrf52/Kconfig index 99990ec37b..bd3d22329d 100644 --- a/arch/arm/src/nrf52/Kconfig +++ b/arch/arm/src/nrf52/Kconfig @@ -17,6 +17,13 @@ config ARCH_CHIP_NRF52832 #select NRF52_HAVE_I2C_MASTER #select NRF52_HAVE_UART +config ARCH_CHIP_NRF52840 + bool "NRF52840" + select ARCH_FAMILY_NRF52 + select ARCH_FAMILY_NRF52840 + #select NRF52_HAVE_I2C_MASTER + #select NRF52_HAVE_UART + endchoice # NRF52 Chip Selection # NRF52 Families @@ -29,6 +36,10 @@ config ARCH_FAMILY_NRF52832 bool default n +config ARCH_FAMILY_NRF52840 + bool + default n + # Peripheral support # Peripheral Selection @@ -63,6 +74,15 @@ config NRF52_UART0 select UART0_SERIALDRIVER select NRF52_HAVE_UART +config NRF52_RNG + bool "Random Generator" + default n + +config NRF52_QSPI + bool "QSPI" + default n + depends on ARCH_CHIP_NRF52840 + config NRF52_WDT bool "Watchdog (WDT)" default n diff --git a/arch/arm/src/nrf52/chip/nrf52832_memorymap.h b/arch/arm/src/nrf52/chip/nrf52832_memorymap.h deleted file mode 100644 index 0e433eb7af..0000000000 --- a/arch/arm/src/nrf52/chip/nrf52832_memorymap.h +++ /dev/null @@ -1,126 +0,0 @@ -/**************************************************************************** - * arch/arm/src/nrf52/chip/nrf52832_memorymap.h - * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Author: Janne Rosberg - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_NRF52_CHIP_NRF52832_MEMORYMAP_H -#define __ARCH_ARM_SRC_NRF52_CHIP_NRF52832_MEMORYMAP_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Memory Map */ - -#define NRF52_FLASH_BASE 0x00000000 /* Flash memory (512 KB) */ -#define NRF52_SRAM_BASE 0x20000000 /* SRAM bank (64 KB) */ -#define NRF52_FICR_BASE 0x10000000 /* FICR */ -#define NRF52_UICR_BASE 0x10001000 /* UICR */ -#define NRF52_APB0_BASE 0x40000000 /* APB */ - -#define NRF52_CORTEXM4_BASE 0xe0000000 /* Cortex-M4 Private Peripheral Bus */ - -/* APB Peripherals */ - -#define NRF52_CLOCK_BASE 0x40000000 -#define NRF52_POWER_BASE 0x40000000 -#define NRF52_BPROT_BASE 0x40000000 -#define NRF52_RADIO_BASE 0x40001000 -#define NRF52_UARTE0_BASE 0x40002000 -#define NRF52_UART0_BASE 0x40002000 -#define NRF52_SPIM0_BASE 0x40003000 -#define NRF52_SPIS0_BASE 0x40003000 -#define NRF52_TWIM0_BASE 0x40003000 -#define NRF52_TWI0_BASE 0x40003000 -#define NRF52_SPI0_BASE 0x40003000 -#define NRF52_TWIS0_BASE 0x40003000 -#define NRF52_SPIM1_BASE 0x40004000 -#define NRF52_TWI1_BASE 0x40004000 -#define NRF52_SPIS1_BASE 0x40004000 -#define NRF52_TWIS1_BASE 0x40004000 -#define NRF52_TWIM1_BASE 0x40004000 -#define NRF52_SPI1_BASE 0x40004000 -#define NRF52_NFCT_BASE 0x40005000 -#define NRF52_GPIOTE_BASE 0x40006000 -#define NRF52_SAADC_BASE 0x40007000 -#define NRF52_TIMER0_BASE 0x40008000 -#define NRF52_TIMER1_BASE 0x40009000 -#define NRF52_TIMER2_BASE 0x4000A000 -#define NRF52_RTC0_BASE 0x4000B000 -#define NRF52_TEMP_BASE 0x4000C000 -#define NRF52_RNG_BASE 0x4000D000 -#define NRF52_ECB_BASE 0x4000E000 -#define NRF52_CCM_BASE 0x4000F000 -#define NRF52_AAR_BASE 0x4000F000 -#define NRF52_WDT_BASE 0x40010000 -#define NRF52_RTC1_BASE 0x40011000 -#define NRF52_QDEC_BASE 0x40012000 -#define NRF52_LPCOMP_BASE 0x40013000 -#define NRF52_COMP_BASE 0x40013000 -#define NRF52_SWI0_BASE 0x40014000 -#define NRF52_EGU0_BASE 0x40014000 -#define NRF52_EGU1_BASE 0x40015000 -#define NRF52_SWI1_BASE 0x40015000 -#define NRF52_SWI2_BASE 0x40016000 -#define NRF52_EGU2_BASE 0x40016000 -#define NRF52_SWI3_BASE 0x40017000 -#define NRF52_EGU3_BASE 0x40017000 -#define NRF52_EGU4_BASE 0x40018000 -#define NRF52_SWI4_BASE 0x40018000 -#define NRF52_SWI5_BASE 0x40019000 -#define NRF52_EGU5_BASE 0x40019000 -#define NRF52_TIMER3_BASE 0x4001A000 -#define NRF52_TIMER4_BASE 0x4001B000 -#define NRF52_PWM0_BASE 0x4001C000 -#define NRF52_PDM_BASE 0x4001D000 -#define NRF52_NVMC_BASE 0x4001E000 -#define NRF52_PPI_BASE 0x4001F000 -#define NRF52_MWU_BASE 0x40020000 -#define NRF52_PWM1_BASE 0x40021000 -#define NRF52_PWM2_BASE 0x40022000 -#define NRF52_SPI2_BASE 0x40023000 -#define NRF52_SPIS2_BASE 0x40023000 -#define NRF52_SPIM2_BASE 0x40023000 -#define NRF52_RTC2_BASE 0x40024000 -#define NRF52_I2S_BASE 0x40025000 -#define NRF52_FPU_BASE 0x40026000 - -#define NRF52_GPIO_P0_BASE 0x50000000 - -#endif /* __ARCH_ARM_SRC_NRF52_CHIP_NRF52832_MEMORYMAP_H */ diff --git a/arch/arm/src/nrf52/chip/nrf52_memorymap.h b/arch/arm/src/nrf52/chip/nrf52_memorymap.h index 9974507a36..ca4a5c2a25 100644 --- a/arch/arm/src/nrf52/chip/nrf52_memorymap.h +++ b/arch/arm/src/nrf52/chip/nrf52_memorymap.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/nrf52/chip/nrf52_memorymap.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. @@ -31,22 +31,103 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_NRF52_CHIP_NRF52_MEMORYMAP_H #define __ARCH_ARM_SRC_NRF52_CHIP_NRF52_MEMORYMAP_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -#if defined(CONFIG_ARCH_FAMILY_NRF52832) -# include "chip/nrf52832_memorymap.h" -#else -# error "Unsupported NRF52 family" -#endif +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Memory Map */ + +#define NRF52_FLASH_BASE 0x00000000 /* Flash memory Start Address */ +#define NRF52_SRAM_BASE 0x20000000 /* SRAM Start Address */ +#define NRF52_FICR_BASE 0x10000000 /* FICR */ +#define NRF52_UICR_BASE 0x10001000 /* UICR */ +#define NRF52_APB0_BASE 0x40000000 /* APB */ + +#define NRF52_CORTEXM4_BASE 0xe0000000 /* Cortex-M4 Private Peripheral Bus */ + +/* APB Peripherals */ + +#define NRF52_CLOCK_BASE 0x40000000 +#define NRF52_POWER_BASE 0x40000000 +#define NRF52_BPROT_BASE 0x40000000 +#define NRF52_RADIO_BASE 0x40001000 +#define NRF52_UARTE0_BASE 0x40002000 +#define NRF52_UART0_BASE 0x40002000 +#define NRF52_SPIM0_BASE 0x40003000 +#define NRF52_SPIS0_BASE 0x40003000 +#define NRF52_TWIM0_BASE 0x40003000 +#define NRF52_TWI0_BASE 0x40003000 +#define NRF52_SPI0_BASE 0x40003000 +#define NRF52_TWIS0_BASE 0x40003000 +#define NRF52_SPIM1_BASE 0x40004000 +#define NRF52_TWI1_BASE 0x40004000 +#define NRF52_SPIS1_BASE 0x40004000 +#define NRF52_TWIS1_BASE 0x40004000 +#define NRF52_TWIM1_BASE 0x40004000 +#define NRF52_SPI1_BASE 0x40004000 +#define NRF52_NFCT_BASE 0x40005000 +#define NRF52_GPIOTE_BASE 0x40006000 +#define NRF52_SAADC_BASE 0x40007000 +#define NRF52_TIMER0_BASE 0x40008000 +#define NRF52_TIMER1_BASE 0x40009000 +#define NRF52_TIMER2_BASE 0x4000a000 +#define NRF52_RTC0_BASE 0x4000b000 +#define NRF52_TEMP_BASE 0x4000c000 +#define NRF52_RNG_BASE 0x4000d000 +#define NRF52_ECB_BASE 0x4000e000 +#define NRF52_CCM_BASE 0x4000f000 +#define NRF52_AAR_BASE 0x4000f000 +#define NRF52_WDT_BASE 0x40010000 +#define NRF52_RTC1_BASE 0x40011000 +#define NRF52_QDEC_BASE 0x40012000 +#define NRF52_LPCOMP_BASE 0x40013000 +#define NRF52_COMP_BASE 0x40013000 +#define NRF52_SWI0_BASE 0x40014000 +#define NRF52_EGU0_BASE 0x40014000 +#define NRF52_EGU1_BASE 0x40015000 +#define NRF52_SWI1_BASE 0x40015000 +#define NRF52_SWI2_BASE 0x40016000 +#define NRF52_EGU2_BASE 0x40016000 +#define NRF52_SWI3_BASE 0x40017000 +#define NRF52_EGU3_BASE 0x40017000 +#define NRF52_EGU4_BASE 0x40018000 +#define NRF52_SWI4_BASE 0x40018000 +#define NRF52_SWI5_BASE 0x40019000 +#define NRF52_EGU5_BASE 0x40019000 +#define NRF52_TIMER3_BASE 0x4001a000 +#define NRF52_TIMER4_BASE 0x4001b000 +#define NRF52_PWM0_BASE 0x4001c000 +#define NRF52_PDM_BASE 0x4001d000 +#define NRF52_NVMC_BASE 0x4001e000 +#define NRF52_PPI_BASE 0x4001f000 +#define NRF52_MWU_BASE 0x40020000 +#define NRF52_PWM1_BASE 0x40021000 +#define NRF52_PWM2_BASE 0x40022000 +#define NRF52_SPI2_BASE 0x40023000 +#define NRF52_SPIS2_BASE 0x40023000 +#define NRF52_SPIM2_BASE 0x40023000 +#define NRF52_RTC2_BASE 0x40024000 +#define NRF52_I2S_BASE 0x40025000 +#define NRF52_FPU_BASE 0x40026000 + +#define NRF52_USBD_BASE 0x40027000 +#define NRF52_UARTE1_BASE 0x40028000 +#define NRF52_QSPI_BASE 0x40029000 +#define NRF52_PWM3_BASE 0x4002d000 +#define NRF52_SPIM3_BASE 0x4002f000 + +#define NRF52_GPIO_P0_BASE 0x50000000 +#define NRF52_GPIO_P1_BASE 0x50003000 #endif /* __ARCH_ARM_SRC_NRF52_CHIP_NRF52_MEMORYMAP_H */ -